PIC18F13K22-I/ML Microchip Technology, PIC18F13K22-I/ML Datasheet - Page 56

• Manufacturer Part Number: PIC18F13K22-I/ML
• Description: IC MCU 8BIT 8KB FLASH 20-QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F13K22-I/ML

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, MSSP, SPI, USART
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F1XK22/LF1XK22
4.5
The programming block size is 8 or 16 bytes, depend-
ing on the device (See Table 4-1). Word or byte pro-
gramming is not supported.
Table writes are used internally to load the holding
registers needed to program the Flash memory. There
are only as many holding registers as there are bytes
in a write block (See Table 4-1).
Since the Table Latch (TABLAT) is only a single byte,
the TBLWT instruction may need to be executed 8, or 16
times, depending on the device, for each programming
operation. All of the table write operations will essen-
tially be short writes because only the holding registers
are written. After all the holding registers have been
written, the programming operation of that block of
memory is started by configuring the EECON1 register
for a program memory write and performing the long
write sequence.
FIGURE 4-5:
4.5.1
The sequence of events for programming an internal
program memory location should be:
1.
2.
3.
4.
5.
6.
7.
DS41365D-page 56
TBLPTR = xxxx00
Read 64 bytes into RAM.
Update data values in RAM as necessary.
Load Table Pointer register with address being
erased.
Execute the block erase procedure.
Load Table Pointer register with address of first
byte being written.
Write the 8 or 16 byte block into the holding
registers with auto-increment.
Set the EECON1 register for the write operation:
• set EEPGD bit to point to program memory;
• clear the CFGS bit to access program memory;
• set WREN to enable byte writes.
Note 1: YY = x7 or xF for 8 or 16 byte write blocks, respectively.
Writing to Flash Program Memory
FLASH PROGRAM MEMORY WRITE
SEQUENCE
Holding Register
8
TABLE WRITES TO FLASH PROGRAM MEMORY
TBLPTR = xxxx01
Holding Register
8
Preliminary
Program Memory
TBLPTR = xxxx02
Write Register
TABLAT
The long write is necessary for programming the inter-
nal Flash. Instruction execution is halted during a long
write cycle. The long write will be terminated by the
internal programming timer.
The EEPROM on-chip timer controls the write time.
The write/erase voltages are generated by an on-chip
charge pump, rated to operate over the voltage range
of the device.
8.
9.
10. Write 0AAh to EECON2.
11. Set the WR bit. This will begin the write cycle.
12. The CPU will stall for duration of the write (about
13. Re-enable interrupts.
14. Repeat steps 6 to 13 for each block until all 64
15. Verify the memory (table read).
This procedure will require about 6 ms to update each
write block of memory. An example of the required code
is given in Example 4-3.
Holding Register
Note:
Note:
Disable interrupts.
Write 55h to EECON2.
2 ms using internal timer).
bytes are written.
8
The default value of the holding registers on
device Resets and after write operations is
FFh. A write of FFh to a holding register
does not modify that byte. This means that
individual bytes of program memory may be
modified, provided that the change does not
attempt to change any bit from a ‘0’ to a ‘1’.
When modifying individual bytes, it is not
necessary to load all holding registers
before executing a long write operation.
Before setting the WR bit, the Table
Pointer address needs to be within the
intended address range of the bytes in the
holding registers.
TBLPTR = xxxxYY
 2010 Microchip Technology Inc.
Holding Register
(1)
8