PIC18F13K22-I/ML Microchip Technology, PIC18F13K22-I/ML Datasheet - Page 249

• Manufacturer Part Number: PIC18F13K22-I/ML
• Description: IC MCU 8BIT 8KB FLASH 20-QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F13K22-I/ML

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, MSSP, SPI, USART
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

21.0
The
between various kinds of Reset:
a)
b)
c)
d)
e)
f)
g)
h)
This section discusses Resets generated by MCLR,
POR and BOR and covers the operation of the various
start-up timers. Stack Reset events are covered in
Section 3.1.2.4 “Stack Overflow and Underflow
Resets”. WDT Resets are covered in Section 22.2
“Watchdog Timer (WDT)”.
FIGURE 21-1:
 2010 Microchip Technology Inc.
OSC1
MCLR
V
Note 1: See Table 21-2 for time-out situations.
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during power-managed modes
Watchdog Timer (WDT) Reset (during
execution)
Programmable Brown-out Reset (BOR)
RESET Instruction
Stack Full Reset
Stack Underflow Reset
DD
PIC18F1XK22/LF1XK22
RESET
2: PWRT and OST counters are reset by POR and BOR. See Sections 21.3 and 21.4.
LFINTOSC
Instruction
RESET
OST/PWRT
Pointer
32 s
Stack
( )_IDLE
Brown-out
Time-out
V
Detect
Sleep
DD
WDT
Reset
Rise
OST
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
PWRT
Stack Full/Underflow Reset
External Reset
MCLRE
10-bit Ripple Counter
11-bit Ripple Counter
(2)
POR Pulse
BOREN
(2)
1024 Cycles
65.5 ms
devices
differentiate
Preliminary
PIC18F1XK22/LF1XK22
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 21-1.
21.1
Device Reset events are tracked through the RCON
register (Register 21-1). The lower five bits of the reg-
ister indicate that a specific Reset event has occurred.
In most cases, these bits can only be cleared by the
event and must be set by the application after the
event. The state of these flag bits, taken together, can
be read to indicate the type of Reset that just occurred.
This is described in more detail in Section 21.6 “Reset
State of Registers”.
The RCON register also has control bits for setting
interrupt priority (IPEN) and software control of the
BOR (SBOREN). Interrupt priority is discussed in
Section 7.0
Section 21.4 “Brown-out Reset (BOR)”.
RCON Register
“Interrupts”.
S
R
BOR
DS41365D-page 249
Q
is
Enable OST
Enable PWRT
Chip_Reset
covered
(1)
in