UDA1345 PHILIPS [NXP Semiconductors], UDA1345 Datasheet

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UDA1345

Manufacturer Part Number
UDA1345
Description
Economy audio CODEC
Manufacturer
PHILIPS [NXP Semiconductors]
Datasheet

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Preliminary specification
Supersedes data of 1999 Dec 02
File under Integrated Circuits, IC01
DATA SHEET
UDA1345TS
Economy audio CODEC
INTEGRATED CIRCUITS
2000 Apr 18

Related parts for UDA1345

UDA1345 Summary of contents

Page 1

... DATA SHEET UDA1345TS Economy audio CODEC Preliminary specification Supersedes data of 1999 Dec 02 File under Integrated Circuits, IC01 INTEGRATED CIRCUITS 2000 Apr 18 ...

Page 2

... The UDA1345TS also supports three combined data formats with MSB justified data output and LSB 16, 18 and 20 bits data input. The UDA1345TS can be used either with static pin control or under L3 microcontroller interface mode the UDA1345TS has basic sound features in playback mode such as de-emphasis, volume control and soft mute ...

Page 3

... A-weighted f = 44.1 kHz kHz s code = 0; A-weighted f = 44.1 kHz kHz Preliminary specification UDA1345TS TYP. MAX. UNIT 3.0 3.6 V 3.0 3.6 V 3.0 3 100 2.5 mA 200 300 A + ...

Page 4

... The input voltage to the ADC scales proportionally with the power supply voltage. 3. The output voltage of the DAC scales proportionally with the power supply voltage. 2000 Apr 18 CONDITIONS MIN. 4 Preliminary specification UDA1345TS TYP. MAX. UNIT ...

Page 5

... SWITCH ADC ADC DECIMATION FILTER DC-CANCELLATION FILTER DIGITAL INTERFACE INTERPOLATION FILTER NOISE SHAPER DAC DAC SSO V DDA(DAC) V SSA(DAC) Fig.1 Block diagram. 5 Preliminary specification UDA1345TS V ADCN V ref( dB/6 dB VINR SWITCH 8 MC1 21 MC2 20 MP5 13 MP2 14 L3-BUS MP3 INTERFACE ...

Page 6

... SSO V 28 analog pad ref(D) 2000 Apr 18 TYPE 6 Preliminary specification UDA1345TS DESCRIPTION ADC analog ground ADC analog supply voltage ADC input left ADC reference voltage ADC input right ADC negative reference voltage ADC positive reference voltage mode control 1 (pull-down) ...

Page 7

... V DDA(DAC) Section “L3 microcontroller mode”). This block can SSA(DAC) used in applications in which both 1 V (RMS) and 2 V (RMS) input signals can be input to the UDA1345TS. 21 MC2 In applications in which (RMS) input signal is used, 20 MP5 resistor must be used in series with the input of the ...

Page 8

... Table 4 Mode Control pins MC1 and MC2 L3MODE Test modes Static pin mode . It shifts s Important: in L3MODE the UDA1345TS is completely pin and function compatible with the UDA1340M and the UDA1344TS. Note: the UDA1345TS does NOT support bass-boost and treble. 8 Preliminary specification UDA1345TS MODE MC2 LOW LOW ...

Page 9

... Attenuation 0.00000036f . s Dynamic range Static pin mode The UDA1345TS is set to static pin control mode by setting both MC1 (pin 8) and MC2 (pin 21) HIGH. P INNING DEFINITION The pinning definition under static pin control is given in Table 7. Table 7 Pinning definition for static pin control ...

Page 10

... The formats are illustrated in Fig.3. Left and right data channel words are time multiplexed. ADC INPUT VOLTAGE CONTROL The UDA1345TS supports (RMS) input using a series resistor as described in Section “Analog front-end”. In static pin mode the 3-level pin MP4 (pin 15) is used to MP2 select gain mode ...

Page 11

Acrobat reader. white to force landscape pages to be ... WS LEFT BCK DATA MSB B2 WS LEFT ...

Page 12

... Data bits represent a 6-bit device address, with bit 7 being the MSB and bit 2 the LSB. The address of the UDA1345TS is 000101 (bit 7 to bit 2). In the event that the UDA1345TS receives a different address, it will deselect its microcontroller interface logic. ...

Page 13

... L3MODE t s(MT) L3CLOCK L3DATA write 2000 Apr s(MA) t s(DAT) t h(DAT) BIT 0 Fig.4 Timing address mode h(DAT) t s(DAT) BIT 0 Fig.5 Timing for data transfer mode. 13 Preliminary specification UDA1345TS t s(MA) t h(MA BIT 7 MGL883 t halt h(MT) t h(DAT) BIT 7 MGL884 ...

Page 14

... VC3 VC2 VC1 VC0 DE0 PC1 PC0 14 Preliminary specification UDA1345TS address MGD018 REGISTER SELECTED System Clock frequency (5 : 4); data Input Format (3 : 1); DC-filter REGISTER SELECTED Volume Control ( not used De-Emphasis (4 : 3); MuTe Power Control ( ...

Page 15

... De-emphasis A 2-bit value to enable the digital de-emphasis filter. Table 19 De-emphasis settings DE1 Mute A 1-bit value to enable the digital DAC mute (playback). FUNCTION Table 20 DAC mute Preliminary specification UDA1345TS VOLUME (dB ...

Page 16

... C; amb amb DD note 2 output short-circuited to V SSA(DAC) output short-circuited to V DDA(DAC) CONDITIONS in free air 16 Preliminary specification UDA1345TS FUNCTION ADC off off on on MIN. MAX. 5.0 150 65 +125 40 +85 according to JEDEC II specification 200 = 3 V; 450 325 VALUE ...

Page 17

... DAC power-down operating mode DAC power-down operating mode ADC and DAC power-down 2.0 0.5 1.3 0.9 0.4 0.9V 0.4V 0 0.85V with respect to V 0.45V SSA kHz i 17 Preliminary specification UDA1345TS MIN. TYP. MAX. 3.0 3.6 V 3.0 3.6 V 3.0 3 100 2.5 mA 200 5.0 mA 300 5.0 V 0 ...

Page 18

... Apr 18 CONDITIONS with respect to V SSA (THD + N)/S < 0.1 800 L note 2 ) must be connected to the same external power supply unit. SS resistor must be connected in series with the DAC output 18 Preliminary specification UDA1345TS MIN. TYP. MAX. 0.45V 0.5V 0.55V DDA DDA DDA 12.5 0.13 3.0 tbf 3 ...

Page 19

... A-weighted f = 44.1 kHz kHz s code = 0; A-weighted f = 44.1 kHz kHz kHz; ripple ripple(p-p) 19 Preliminary specification UDA1345TS MIN. TYP. MAX. UNIT 1 100 dB 30 ...

Page 20

... MHz sys f 19.2 MHz sys f < 19.2 MHz sys f 19.2 MHz sys address mode address mode data transfer mode data transfer mode 20 Preliminary specification UDA1345TS MIN. TYP. MAX. UNIT 39 88 781 520 390 ns 0.30T 0.70T ns sys sys ...

Page 21

... CWL T sys Fig.7 System clock timing. t s(WS) t h(WS BCKL t d(DATAO-WS) Fig.8 Serial interface timing. 21 Preliminary specification UDA1345TS MIN. TYP. MAX. 190 30 190 MGR984 t d(DATAO-BCK) t h(DATAO) t s(DATAI) t h(DATAI) MGL885 UNIT ...

Page 22

... MP2 13 MP3 14 MP4 SSO V DDO C26 100 nF ( 100 F R25 ( DDO Fig.9 Application diagram. 22 Preliminary specification UDA1345TS V DDD R28 10 V ADCP V SSD V DDD ref(A) 4 C22 100 nF ( VOUTL R22 ( ...

Page 23

... Apr 2.5 scale (1) ( 0.38 0.20 10.4 5.4 7.9 0.65 0.25 0.09 10.0 5.2 7.6 REFERENCES JEDEC EIAJ MO-150 23 Preliminary specification detail 1.03 0.9 1.25 0.2 0.13 0.63 0.7 EUROPEAN PROJECTION UDA1345TS SOT341 ( 1.1 8 0.1 o 0.7 0 ISSUE DATE 95-02-04 99-12-27 ...

Page 24

... Use a low voltage ( less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds 300 C. When using a dedicated tool, all other leads can be soldered in one operation within seconds between 270 and 320 C. 24 Preliminary specification UDA1345TS ...

Page 25

... Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2000 Apr 18 SOLDERING METHOD WAVE not suitable (2) not suitable suitable (3)(4) not recommended (5) not recommended 25 Preliminary specification UDA1345TS (1) REFLOW suitable suitable suitable suitable suitable ...

Page 26

... Preliminary specification UDA1345TS (1) These products are not Philips Semiconductors ...

Page 27

... Philips Semiconductors Economy audio CODEC 2000 Apr 18 NOTES 27 Preliminary specification UDA1345TS ...

Page 28

Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. + 101 ...

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