UDA1345 PHILIPS [NXP Semiconductors], UDA1345 Datasheet - Page 9

• Manufacturer Part Number: UDA1345
• Description: Economy audio CODEC
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
L3 microcontroller mode
The UDA1345TS is set to the L3 microcontroller mode by
setting both MC1 (pin 8) and MC2 (pin 21) LOW.
The definition of the control registers is given in Section
“L3 interface”.
P
The pinning definition under L3 microcontroller interface is
given in Table 5.
Table 5 Pinning definition under L3 control
S
Under L3 control the options are 256, 384 and 512f
M
The UDA1345TS supports the following data input/output
formats under L3 control:
The formats are illustrated in Fig.3. Left and right data
channel words are time multiplexed.
ADC
The UDA1345TS supports a 2 V (RMS) input using a
series resistor of 12 k as described in Section “Analog
front-end”. In L3 microcontroller mode, the gain can be
selected via pin MP5.
When MP5 is set LOW, 0 dB gain is selected. When MP5
is set HIGH, 6 dB gain is selected.
2000 Apr 18
SYMBOL
INNING DEFINITION
YSTEM CLOCK
ULTIPLE FORMAT INPUT
I
MSB-justified serial format with data word length of up to
20 bits
LSB-justified serial format with data word lengths of
16, 18 or 20 bits
Three combined data formats with MSB data output and
LSB 16, 18 and 20 bits data input.
Economy audio CODEC
2
MP1
MP2
MP3
MP4
MP5
S-bus with data word length of up to 24 bits
INPUT VOLTAGE CONTROL
PIN
13
14
15
20
9
OVERFL output
L3MODE input
L3CLOCK input
L3DATA input
ADC 1 or 2 V (RMS) input control
/
OUTPUT INTERFACE
DESCRIPTION
s
.
9
O
In practice the output is used to indicate whenever the
output data, in either the left or right channel, is greater
than 1 dB (the actual figure is 1.16 dB) of the maximum
possible digital swing. When this condition is detected the
OVERFL output is forced HIGH for at least 512f
(11.6 ms at f
infringement.
DC
An optional IIR high-pass filter is provided to remove
unwanted DC components. The operation is selected by
the microcontroller via the L3-bus. The filter characteristics
are given in Table 6.
Table 6 DC cancellation filter characteristics
Static pin mode
The UDA1345TS is set to static pin control mode by setting
both MC1 (pin 8) and MC2 (pin 21) HIGH.
P
The pinning definition under static pin control is given in
Table 7.
Table 7 Pinning definition for static pin control
Pass-band ripple
Pass-band gain
Droop
Attenuation at DC
Dynamic range
MP1
MP2
MP3
MP4
MP5
SYMBOL
INNING DEFINITION
VERLOAD DETECTION
CANCELLATION FILTER
ITEM
s
= 44.1 kHz). This time-out is reset for each
PIN
13
14
15
20
9
data input/output setting
3-level pin controlling de-emphasis
and mute
256f
3-level pin to control ADC power
mode and 1 V (RMS) or 2 V (RMS)
input
data input/output setting
at 0.00000036f
(ADC)
CONDITIONS
at 0.00045f
s
(ADC)
0
or 384f
0.45f
DESCRIPTION
Preliminary specification
s
s
system clock
s
UDA1345TS
s
VALUE (dB)
0.031
none
>110
>40
s
0
cycles