LTC1343 Linear Technology, LTC1343 Datasheet
LTC1343
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LTC1343 Summary of contents
Page 1
... LTC1344 software-selectable cable termination chip or by using existing discrete designs. The LTC1343 runs from a single 5V supply using an internal charge pump that requires only five space saving surface mount capacitors. The mode pins are latched internally to allow sharing of the select lines between multiple interface ports ...
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... Short-Circuit Duration Transmitter Output ..................................... Indefinite Receiver Output .......................................... Indefinite V .................................................................. 30 sec EE Operating Temperature Range LTC1343C .............................................. LTC1343I ........................................... – Storage Temperature Range ................ – 150 C Lead Temperature (Soldering, 10 sec)................. 300 C ELECTRICAL CHARACTERISTICS temperature range, otherwise specifications are at T SYMBOL PARAMETER Supplies ...
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... V 10V A, B – 10V V 10V A, B (Figures 2, 7) (Figures 2, 7), CTRL = GND CTRL = (Figures 2, 7), CTRL = GND, – CTRL = V , – LTC1343 MIN TYP MAX 4.5 0.3 0.8 – – ...
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... LTC1343 ELECTRICAL CHARACTERISTICS temperature range, otherwise specifications are at T SYMBOL PARAMETER t Input to Output PHL t Input to Output Difference, t PLH V.35 Driver V Differential Output Voltage OD I Transmitter Output High Current OH I Transmitter Output Low Current OL I Transmitter Output Leakage Current Rise or Fall Time ...
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... Capacitor C1 Negative Terminal. D1 (Pin 5): TTL Level Driver 1 Input. D2 (Pin 6): TTL Level Driver 2 Input. – (Pin 7): TTL Level Driver 3 Input. Becomes a CMOS level output when the chip is in the echoed clock mode (Pin 8) and bypass CC (EC = 0V). LTC1343 MIN TYP MAX – 0.2 0 – 0.3 0 ...
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... LTC1343 PIN FUNCTIONS V (Pin 8): Positive Supply for the Transceivers. 4.75V CC V 5.25V. Tie to PWRV (Pin 3 (Pin 9): TTL Level Driver 4 Input. D4EN (Pin 10): TTL Level Enable Input for Driver 4. When high, driver 4 outputs are enabled. When low, driver 4 outputs are forced into a high impedance state. D4EN is not affected by the LATCH pin ...
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... Figure 1. RS422 Driver Test Circuit Figure 4. V.10/V.28 Driver Test Circuit W U ODE SELECTIO LTC1343 MODE NAME M2 M1 V.10, RS423 0 0 EIA-530-A Clock and Data 0 0 EIA-530-A Control 0 0 Reserved V.35 Clock and Data 1 0 V.35 Control ...
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... LTC1343 U W SWITCHI WAVEFOR PLH B – 50% – OD2 B – –V OD2 t PLH 1. PHL – 1. PHL 1MHz : t 10ns : t 10ns V(A) – ...
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... A complete DCE-to-DTE interface operating in EIA-530 mode is shown in Figure 10. The first LTC1343 of each port is used to generate the clock and data signals along with LL (Local Loop-back) and TM (Test Mode). The second LTC1343 is used to generate the control signals along with ...
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... Figure 11. The pull-up resistors R1 through R4 will ensure a binary 1 when a pin is left unconnected and that the two LTC1343s and the LTC1344 enter the no-cable mode when the cable is removed. In the no-cable mode the LTC1343 supply ...
Page 11
... PORT #1 supply voltage for the FET drivers or the power is off. Using the LTC1344 along with the LTC1343 solves the cable termination switching problem. Via software con- trol, the LTC1344 provides termination for the V.10 (RS423), V ...
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... INFORMATION The V.10 receiver configuration in the LTC1343 and LTC1344 is shown in Figure 15. In V.10 mode switches S1 and S2 inside the LTC1344 and S3 inside the LTC1343 are turned off. Switch S4 inside the LTC1343 shorts the noninverting receiver input to ground so the B input at the connector can be left floating. The cable termination is then the 30k input impedance to ground of the LTC1343 V ...
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... In V.35 mode, both switches S1 and S2 inside the LTC1344 are on, connecting the T network impedance as shown in Figure 21. Both switches in the LTC1343 are off. The 30k input impedance of the receiver is placed in parallel with the T network termination, but does not affect the overall input impedance significantly. ...
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... W U Loop-Back The LTC1343 contains logic for placing the interface into a loop-back configuration for testing. Both DTE and DCE loop-back configurations are supported. Figure 24 shows a complete DTE interface in the loop-back configuration with the EC pin pulled high. The loop-back configuration is selected by pulling the LB pin low. Both the line side and logic side signals are looped back ...
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... DCD DSR DSR CTS CTS RI RI 1343 F24 LTC1343 LTC1343 R4 R3 103 103 LTC1343 Figure 25. Normal DCE Loop-Back SERIAL CONTROLLER LL TXD SCTE TXC RXC RXD TM RL ...
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... DSR DSR CTS CTS 1343 F26 LTC1344 LTC1343 R4 R3 103 103 LTC1343 Figure 27. Echoed Clock, DCE Loop-Back SERIAL CONTROLLER LL RXD RXC TXC TXD TM RL RTS ...
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... The graph of Driver Rise and Fall Times vs Resistor Value is shown in Figure 29. Enabling the Single-Ended Driver and Receiver When the LTC1343 is being used to generate the control signals (CTRL/CLK = high) and the EC pin is pulled low, the DCE/DTE pin becomes an enable for driver 1 and receiver 4 so their inputs and outputs can be tied together as shown in Figure 30 ...
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... DTE or DCE operation. For example, in DTE mode, the TXD signal is routed to connector Pins 2 and 14 via driver 2 in the LTC1343. In DCE mode, driver 2 now routes the RXD signal to Pins 2 and 14. A combination DTE/DCE port that doesn’t require separate DCE/DTE cables is shown in Figure 34 ...
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... DCE LTC1343 13 LTC1344 21 LATCH LATCH DB-25 MALE DCE/ CONNECTOR DTE (141) 2 TXD A (103) 14 TXD B 24 SCTE A (113) 11 SCTE B 15 TXC A (114) ...
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... DCE C10 CHARGE C13 PUMP 3 LTC1343 DCE LTC1344 21 LATCH ...
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... DCE CTRL LATCH INVERT 423 SET 40 GND LTC1343 LTC1344 21 LATCH LATCH DB-25 CONNECTOR DCE/ DTE DTE TXD A 14 TXD B 24 SCTE A 11 ...
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... TXD LTC1343 CTS DSR 21 DCE DCD DTR 15 RTS LTC1343 DCE Figure 34. Controller-Selectable Multiprotocol DTE/DCE Port with DB- 100pF 100pF 100pF ...
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... DCE LTC1343 13 LTC1344 21 LATCH LATCH DB-25 MALE DCE/ CONNECTOR DTE (141) 2 TXD A (103) 14 TXD B 24 SCTE A (113) 11 SCTE B 15 TXC A (114) ...
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... DCE C10 CHARGE C13 PUMP 3 LTC1343 DCE RIEN = RS232 LTC1344 21 LATCH LATCH DB-25 FEMA ...
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... R4 21 DCE CTRL LATCH INVERT 17 423 SET M0 CABLE WIRING FOR MODE SELECTION GND MODE V.35 EIA-530, RS449, V.36, X.21 RS232 LTC1343 12 13 LTC1344 21 LATCH DB-25 CONNECTOR DCE/ DTE DTE CC 2 TXD A 14 TXD B 24 ...
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... DCE CTRL 19 LATCH M2 18 INVERT M1 17 423 SET M0 GND C10 CHARGE C13 PUMP 3 LTC1343 DCE CTRL 19 M2 LATCH 18 M1 INVERT 17 M0 423 SET ...
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... R4 21 DCE CTRL LATCH INVERT 17 M0 423 SET CABLE WIRING FOR MODE SELECTION GND MODE V.35 EIA-530, RS449, V.36, X.21 RS232 LTC1343 13 12 LTC1344 21 LATCH DB-26 CONNECTOR DCE/ DTE DTE CC 2 TXD A 14 TXD B 24 ...
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... FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE COMMENTS 2 RS232 Driver/Receiver Pairs or 2 RS485 Driver/Receiver Pairs 2 RS232 Driver/Receiver or 4 RS232 Driver/Receiver Pairs Perfect for Terminating the LTC1343 3 Driver/3 Receiver for Data and Clock Signals 3 Driver/3 Receiver for Data and Clock Signals 3 Driver/3 Receiver for Data and Clock Signals ...