LTC1343 Linear Technology, LTC1343 Datasheet - Page 17

• Manufacturer Part Number: LTC1343
• Description: Software-Selectable Multiprotocol Transceiver
• Manufacturer: Linear Technology

APPLICATIONS
No-Cable Mode
The no-cable mode (M0 = M1 = M2 = 1) is intended for the
case when the cable is disconnected from the connector.
The charge pump, bias circuitry, drivers and receivers are
turned off, the driver outputs are forced into a high
impedance state, and the supply current drops to less than
200 A. It can also be used to share I/O lines with other
drivers and receivers without loading down the signals.
Charge Pump
The LTC1343 uses an internal capacitive charge pump to
generate V
doubler generates about 8V on V
generates about – 7.5V for V
tantalum or ceramic capacitors are required for C1, C2, C3
and C4. The V
3.3 F. All capacitors are 16V.
Receiver Fail-Safe and Glitch Filter
All LTC1343 receivers feature fail-safe operation in all
modes except no-cable mode. If the receiver inputs are left
floating or shorted together by a termination resistor, the
receiver output will always be forced to a logic high.
External pull-up resistors are required on receiver outputs
if fail-safe operation in the no-cable mode is desired.
When the chip is configured for control signals by pulling
the CTRL/CLK pin high, a glitch filter is connected to all
receiver inputs. The filter will reject any glitches at the
receiver inputs less than 300ns.
V.10 Driver Rise and Fall Times
The rise and fall times of the V.10 drivers is programmed
by placing a 1/8W, 5% resistor between the 423 SET (Pin
25) and ground. The graph of Driver Rise and Fall Times
vs Resistor Value is shown in Figure 29.
Enabling the Single-Ended Driver and Receiver
When the LTC1343 is being used to generate the control
signals (CTRL/CLK = high) and the EC pin is pulled low, the
DCE/DTE pin becomes an enable for driver 1 and receiver
4 so their inputs and outputs can be tied together as shown
in Figure 30.
DD
and V
EE
capacitor C5 should be a minimum of
U
EE
as shown in Figure 28. A voltage
INFORMATION
U
EE
. Four 1 F surface mounted
DD
W
and a voltage inverter
U
Figure 29. V.10 Driver Rise and Fall Time vs Resistor Value
+
5V
Figure 30. Single-Ended Driver and Receiver Enable
DCE/DTE
C4
1 F
+
V
100
CC
0.1
10
1
C3
1 F
1k
+
Figure 28. Charge Pump
21
16
20
24
5
C1
1 F
CTRL/CLK
EC
10k
1
2
3
4
8
RESISTANCE ( )
V
C1
PWRV
C1
V
LTC1343
DD
CC
D1
+
–
R4
CC
100k
LTC1343
PGND
GND
39
26
C2
C2
V
1343 F30
1M
EE
+
–
44
43
42
41
40
1343 F29
LTC1343
5M
+
+
17
C5
3.3 F
1343 F28
C2
1 F