ISL6313B Intersil Corporation, ISL6313B Datasheet - Page 21

• Manufacturer Part Number: ISL6313B
• Description: Two-Phase Buck PWM Controller
• Manufacturer: Intersil Corporation

from shutdown mode to begin the soft-start start-up
sequence:
For Intel VR11 and AMD 6-bit modes of operation these are
the only conditions that must be met for the controller to
immediately begin the soft-start sequence. If running in AMD
5-bit mode of operation there is one more condition that
must be met:
Once all of these conditions are met the controller will begin
the soft-start sequence and will ramp the output voltage up
to the user designated level.
Intel Soft-Start
The soft-start function allows the converter to bring up the
output voltage in a controlled fashion, resulting in a linear
ramp-up. The soft-start sequence for the Intel modes of
operation is slightly different then the AMD soft-start
sequence.
For the Intel VR11 mode of operation, the soft-start
sequence if composed of four periods, as shown in
Figure 21. Once the ISL6313B is released from shutdown
and soft-start begins (as described in “Enable and Disable”
on page 20), the controller will have a fixed delay period T
of typically 1.10ms. After this delay period, the VR will begin
first soft-start ramp until the output voltage reaches 1.1V
VBOOT voltage. Then, the controller will regulate the VR
voltage at 1.1V for another fixed delay period t
93µs. At the end of t
signals. It is recommended that the VID codes be set no
later then 50µs into period t
ISL6313B will initiate the second soft-start ramp until the
1. The bias voltage applied at VCC must reach the internal
2. The voltage on EN must be above 0.85V. The EN input
3. The driver bias voltage applied at the PVCC pin must
4. The VID code must not be 11111 in AMD 5-bit mode. This
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power-on reset (POR) rising threshold. Once this
threshold is reached, proper operation of all aspects of
the ISL6313B is guaranteed. Hysteresis between the
rising and falling thresholds assure that once enabled,
the ISL6313B will not inadvertently turn off unless the
bias voltage drops substantially (see Electrical
Specifications on page 6).
allows for power sequencing between the controller bias
voltage and another voltage rail. The enable comparator
holds the ISL6313B in shutdown until the voltage at EN
rises above 0.85V. The enable comparator has 110mV of
hysteresis to prevent bounce.
reach the internal power-on reset (POR) rising threshold.
Hysteresis between the rising and falling thresholds
assure that once enabled, the ISL6313B will not
inadvertently turn off unless the PVCC bias voltage drops
substantially (see Electrical Specifications on page 6).
code signals the controller that no load is present. The
controller will not allow soft-start to begin if this VID code
is present on the VID pins.
d3,
period, ISL6313B will read the VID
d3,
21
. If the VID code is valid,
d3,
of typically
d1
ISL6313B
output voltage reaches the VID voltage plus/minus any offset
or droop voltage.
The soft-start time is the sum of the 4 periods as shown in
Equation 19.
During t
voltage change at 6.25mV per step. The time for each step is
determined by the frequency of the soft-start oscillator which
is defined by the resistor R
soft-start ramp time t
Equations 20 and 21:
For example, when VID is set to 1.5V and the R
100kΩ, the first soft-start ramp time t
second soft-start ramp time t
After the DAC voltage reaches the final VID setting, PGOOD
will be set to high with the fixed delay t
for t
AMD Soft-Start
For the AMD 5-bit and 6-bit modes of operation, the
soft-start sequence is composed of two periods, as shown in
Figure 14. At the beginning of soft-start, the VID code is
immediately obtained from the VID pins, followed by a fixed
delay period t
the ISL6313B will begin ramping the output voltage to the
desired DAC level at a fixed rate of 6.25mV per step. The
time for each step is determined by the frequency of the
soft-start oscillator which is defined by the resistor R
the SS pin. The amount of time required to ramp the output
t
t
t
SS
d2
d4
d5
=
=
=
1.1 R
t
V
is 93µs.
d1
d2
VID
⋅
+
and t
FIGURE 13. SOFT-START WAVEFORMS
t
–
SS
d2
1.1
dA
+
⋅
V
d4
8 10
t
of typically 1.10ms. After this delay period
OUT
d3
⋅
t
⋅
, ISL6313B digitally controls the DAC
d1
R
PGOOD
+
SS
, 500mV/DIV
d2
EN
–
t
d4
3
⋅
(
and t
8 10
μs
⋅
t
)
d2
SS
d4
500µs/DIV
d4
–
3
on the SS pin. The second
will be 320µs.
(
can be calculated based on
μs
t
d3
)
d2
t
d4
d5
will be 880µs and the
. The typical value
t
d5
November 6, 2008
SS
is set at
SS
(EQ. 19)
(EQ. 20)
(EQ. 21)
FN6809.0
on