IDT70261S Integrated Device Technology, IDT70261S Datasheet

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IDT70261S

Manufacturer Part Number
IDT70261S
Description
High-speed 16k X 16 Dual-port Static Ram With Interrupt
Manufacturer
Integrated Device Technology
Datasheet

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©2000 Integrated Device Technology, Inc.
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY and INT outputs are non-tri-stated push-pull.
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed access
– Commercial: 15/20/25/35/55ns (max.)
– Industrial 20/25/35/55ns (max.)
Low-power operation
– IDT70261S
– IDT70261L
Separate upper-byte and lower-byte control for multiplexed
bus compatibility
Active: 750mW (typ.)
Standby: 5mW (typ.)
Active: 750mW (typ.)
Standby: 1mW (typ.)
I/O
I/O
BUSY
8L
0L
INT
-I/O
SEM
R/W
-I/O
UB
A
OE
CE
LB
L
A
(1,2)
13L
L
15L
0L
(2)
L
7L
L
L
L
L
L
Decoder
Address
R/ W
OE
CE
L
L
L
HIGH-SPEED
16K x 16 DUAL-PORT
STATIC RAM WITH INTERRUPT
14
Control
I/O
ARBITRATION
SEMAPHORE
INTERRUPT
MEMORY
ARRAY
LOGIC
M/ S
1
IDT70261 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device
M/S = H for BUSY output flag on Master,
M/S = L for BUSY input on Slave
Busy and Interrupt Flags
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 5V (±10%) power supply
Available in 100-pin Thin Quad Flatpack
Industrial temperature range (-40
for selected speeds
Control
I/O
14
Decoder
Address
CE
OE
R/ W
R
R
R
O
C to +85
IDT70261S/L
3039 drw 01
INT
SEM
O
BUSY
R/W
UB
CE
I/O
A
A
LB
OE
I/O
C) is available
13R
0R
R
R
R
8R
R
0R
(2)
R
R
R
-I/O
-I/O
R
(1,2)
15R
7R
DSC 3039/8

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IDT70261S Summary of contents

Page 1

... True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed access – Commercial: 15/20/25/35/55ns (max.) – Industrial 20/25/35/55ns (max.) Low-power operation – IDT70261S Active: 750mW (typ.) Standby: 5mW (typ.) – IDT70261L Active: 750mW (typ.) Standby: 1mW (typ.) Separate upper-byte and lower-byte control for multiplexed ...

Page 2

... IDT70261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt The IDT70261 is a high-speed 16K x 16 Dual-Port Static RAM. The IDT70261 is designed to be used as a stand-alone Dual-Port RAM combination MASTER/SLAVE Dual-Port RAM for 32-bit-or-more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 32- bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic ...

Page 3

... IDT70261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Ambient Grade Temperature Commercial + Industrial - + NOTES: 1. This is the parameter (1) Inputs ...

Page 4

... IDT70261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Symbol Rating (2) V Terminal Voltage TERM with Respect to GND T Temperature BIAS Under Bias T Storage STG Temperature I DC Output OUT Current NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied ...

Page 5

... IDT70261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Symbol Parameter CE I Dynamic Operating Current CC SEM (Both Ports Active Standby Current SB1 SEM (Both Ports - TTL Level Inputs Standby Current SB2 (One Port - TTL Level Inputs) Active Port Outputs Open, ...

Page 6

... IDT70261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Symbol READ CYCLE t Read Cycle Time RC t Address Access Time AA (3) t Chip Enable Access Time ACE (3) t Byte Enable Access Time ABE t Output Enable Access Time AOE t Output Hold from Address Change ...

Page 7

... IDT70261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt ADDR DATA OUT BUSY OUT NOTES: 1. Timing depends on which signal is asserted last, OE, CE, LB, or UB. 2. Timing depends on which signal is de-asserted first CE, OE, LB, or UB. delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY 3 ...

Page 8

... IDT70261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Symbol Parameter WRITE CYCLE t Write Cycle Time WC (3) t Chip Enable to End-of-Write EW t Address Valid to End-of-Write AW (3) t Address Set-up Time AS t Write Pulse Width WP t Write Recovery Time WR t Data Valid to End-of-Write ...

Page 9

... IDT70261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt ADDRESS OE (9) CE SEM (4) DATA OUT DATA IN ADDRESS (9) CE SEM DATA IN NOTES and during all address transitions write occurs during the overlap (t ...

Page 10

... IDT70261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt VALID ADDRESS SEM I R/W OE NOTES and for the duration of the above timing (both write and read cycle "DATA VALID" represents all I/O's (I/O -I/O OUT 0 A 0"A" ...

Page 11

... IDT70261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Symbol BUSY S TIMING ( BUSY t Access Time from Address Match BAA BUSY t Disable Time from Address Not Matched BDA BUSY t Acce ss Time from Chip Enable Low BAC BUSY t Acce ss Time from Chip Enable High ...

Page 12

... IDT70261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt ADDR "A" "A" DATA IN "A" (1) t APS ADDR "B" BUSY "B" DATA OUT "B" NOTES ensure that the earlier of the two ports wins ...

Page 13

... IDT70261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt BUSY ADDR "A" and "B" +- "A" (2) t APS +- "B" *75; "B" BUSY ADDR "A" t APS ADDR "B" BUSY "B" NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”. ...

Page 14

... IDT70261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt ADDR "A" ( "A" "A" INT "B" ADDR "B" ( "B" OE "B" INT "B" NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”. ...

Page 15

... IDT70261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt BUSY Inputs Outputs 13L CE CE BUSY ( 13R MATCH MATCH MATCH MATCH (2) NOTES: 1. Pins BUSY and BUSY are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT70261 are ...

Page 16

... IDT70261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RAM is “Busy”. ...

Page 17

... IDT70261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt that semaphore’s status or remove its request for that semaphore to perform another task and occasionally attempt again to gain control of the token via the set and test sequence. Once the right side has relinquished the token, the left side should succeed in gaining control ...

Page 18

... IDT70261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt of the resource after the left processor, it would read back a one in response to the zero it had attempted to write into Semaphore 0. At this point, the software could choose to try and gain control of the second 8K section by writing, then reading a zero into Semaphore 1 ...

Page 19

... IDT70261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt IDT XXXXX A 999 Device Power Speed Type 1/14/99: Initiated datasheet document history Converted to new format Cosmetic and typographical corrections Pages 2 Added additional notes to pin configurations 6/4/99: Changed drawing format Page 1 Corrected DSC number 2/18/00: Added Industrial Temperature Ranges and removed related notes Replaced IDT logo Changed ± ...

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