IDT70261S Integrated Device Technology, IDT70261S Datasheet - Page 18

• Manufacturer Part Number: IDT70261S
• Description: High-speed 16k X 16 Dual-port Static Ram With Interrupt
• Manufacturer: Integrated Device Technology

of the resource after the left processor, it would read back a one in response
to the zero it had attempted to write into Semaphore 0. At this point, the
software could choose to try and gain control of the second 8K section by
writing, then reading a zero into Semaphore 1. If it succeeded in gaining
control, it would lock out the left side.
Semaphore 0 and may then try to gain access to Semaphore 1. If
Semaphore 1 was still occupied by the right side, the left side could undo
its semaphore request and perform other tasks until it was able to write, then
read a zero into Semaphore 1. If the right processor performs a similar task
with Semaphore 0, this protocol would allow the two processors to swap
8K blocks of Dual-Port RAM with each other.
variable, depending upon the complexity of the software using the
semaphore flags. All eight semaphores could be used to divide the Dual-
Port RAM or other shared resources into eight parts. Semaphores can
even be assigned different meanings on different sides rather than being
given a common meaning as was shown in the example above.
interfaces where the CPU must be locked out of a section of memory during
IDT70261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt
Once the left side was finished with its task, it would write a one to
The blocks do not have to be any particular size and can even be
Semaphores are a useful form of arbitration in systems like disk
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a transfer and the I/O device cannot tolerate any wait states. With the use
of semaphores, once the two devices has determined which memory area
was “off-limits” to the CPU, both the CPU and the I/O devices could access
their assigned portions of memory continuously without any wait states.
state is available on one or both sides. Once a semaphore handshake has
been performed, both processors can access their assigned RAM
segments at full speed.
case, block arbitration is very important. For this application one processor
may be responsible for building and updating a data structure. The other
processor then reads and interprets that data structure. If the interpreting
processor reads an incomplete data structure, a major error condition may
exist. Therefore, some sort of arbitration must be used between the two
different processors. The building processor arbitrates for the block, locks
it and then is able to go in and update the data structure. When the update
is completed, the data structure block is released. This allows the
interpreting processor to come back and read the complete data structure,
thereby guaranteeing a consistent data structure.
Semaphores are also useful in applications where no memory “WAIT”
Another application is in the area of complex data structures. In this
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