IDT70261S Integrated Device Technology, IDT70261S Datasheet - Page 15

• Manufacturer Part Number: IDT70261S
• Description: High-speed 16k X 16 Dual-port Static Ram With Interrupt
• Manufacturer: Integrated Device Technology

NOTES:
1. Pins BUSY
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
3. Writes to the left port are internally ignored when BUSY
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70261.
2. There are eight semaphore flags written to via I/O
3. CE = V
I/O pins that permit independent access for reads or writes to any location
in memory. The IDT70261 has an automatic power down feature
controlled by CE. The CE controls on-chip power down circuitry that
permits the respective port to go into a standby mode when not selected
(CE = V
is permitted.
or message center) is assigned to each port. The left port interrupt flag
No Action
Le ft Port Writes "0" to Semaphore
Rig ht Port Writes "0" to Semaphore
Le ft Port Writes "1" to Semaphore
Le ft Port Writes "0" to Semaphore
Rig ht Port Writes "1" to Semaphore
Le ft Port Writes "1" to Semaphore
Rig ht Port Writes "0" to Semaphore
Rig ht Port Writes "1" to Semaphore
Le ft Port Writes "0" to Semaphore
Le ft Port Writes "1" to Semaphore
IDT70261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt
CE
X
X
H
L
push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
and enable inputs of this port. If t
when BUSY
The IDT70261 provides two ports with separate control, address and
If the user chooses the interrupt function, a memory location (mail box
L
IH
CE
). When a port is enabled, access to the entire memory array
IH,
X
X
H
L
R
Inputs
SEM = V
L
R
and BUSY
Functions
outputs are driving LOW regardless of actual logic level on the pin.
BUSY
NO MATCH
A
A
MATCH
MATCH
MATCH
OL
OR
IL
-A
-A
to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
R
13L
13R
are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT70261 are
APS
BUSY
is not met, either BUSY
(2)
H
H
H
L
Outputs
(1)
D0 - D15 Left
BUSY
0
1
1
1
1
1
1
1
(2)
0
0
0
0
H
H
H
and read from all I/O's (I/O
L
R
outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
(1)
L
or BUSY
Write Inhibit
Function
D
Normal
Normal
Normal
0
- D
15
R
3039 tbl 17
1
1
1
0
0
1
1
0
1
1
1
= LOW will result. BUSY
Right
(3)
6.42
15
0
-I/O
(INT
(HEX), where a write is defined as CE
III. The left port clears the interrupt through access of address location
3FFE when CE
port interrupt flag (INT
location 3FFF (HEX) and to clear the interrupt flag (INT
must read the memory location 3FFF. The message (16 bits) at 3FFE or
3FFF is user-defined since it is an addressable SRAM location. If the
interrupt function is not used, address locations 3FFE and 3FFF are not
used as mail boxes, but as part of the random access memory. Refer to
Truth Table III for the interrupt operation.
Semaphore free
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
15
L
). These eight semaphores are addressed by A
) is asserted when the right port writes to memory location 3FFE
L
L
Industrial and Commercial Temperature Ranges
and BUSY
= OE
R
L
) is asserted when the left port writes to memory
= V
R
IL
outputs can not be LOW simultaneously.
, R/W is a "don't care". Likewise, the right
Status
R
= R/W
0
R
- A
= V
2
.
IL
per Truth Table
R
), the right port
3039 tbl 18