DS90C385 National Semiconductor, DS90C385 Datasheet

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DS90C385

Manufacturer Part Number
DS90C385
Description
+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-85 MHz/ +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) L
Manufacturer
National Semiconductor
Datasheet

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© 1999 National Semiconductor Corporation
DS90C385/DS90C365
+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel
Display (FPD) Link-85 MHz, +3.3V Programmable LVDS
Transmitter 18-Bit Flat Panel Display (FPD) Link-85 MHz
General Description
The DS90C385 transmitter converts 28 bits of CMOS/TTL
data into four LVDS (Low Voltage Differential Signaling) data
streams. A phase-locked transmit clock is transmitted in par-
allel with the data streams over a fifth LVDS link. Every cycle
of the transmit clock 28 bits of input data are sampled and
transmitted. At a transmit clock frequency of 85 MHz, 24 bits
of RGB data and 3 bits of LCD timing and control data
(FPLINE, FPFRAME, DRDY) are transmitted at a rate of 595
Mbps per LVDS data channel. Using a 85 MHz clock, the
data throughput is 297.5 Mbytes/sec. Also available is the
DS90C365 that converts 21 bits of CMOS/TTL data into
three LVDS (Low Voltage Differential Signaling) data
streams. Both transmitters can be programmed for Rising
edge strobe or Falling edge strobe through a dedicated pin.
A Rising edge or Falling edge strobe transmitter will interop-
erate with a Falling edge strobe Receiver (DS90CF386/
DS90CF366) without any translation logic.
This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
Block Diagrams
TRI-STATE
®
is a registered trademark of National Semiconductor Corporation.
See NS Package Number MTD56
Order Number DS90C385MTD
DS90C385
DS100868
DS100868-1
Features
n 20 to 85 MHz shift clock support
n Best–in–Class Set & Hold Times on TxINPUTs
n Tx power consumption
n Tx Power-down mode
n Supports VGA, SVGA, XGA and Single/Dual Pixel
n Narrow bus reduces cable size and cost
n Up to 2.38 Gbps throughput
n Up to 297.5 Megabytes/sec bandwidth
n 345 mV (typ) swing LVDS devices for low EMI
n PLL requires no external components
n Compatible with TIA/EIA-644 LVDS standard
n Low profile 56-lead or 48-lead TSSOP package
Grayscale
SXGA.
See NS Package Number MTD48
Order Number DS90C365MTD
DS90C365
<
<
200µW (max)
130 mW (typ)
@
85MHz
January 1999
DS100868-29
www.national.com

Related parts for DS90C385

DS90C385 Summary of contents

Page 1

... Display (FPD) Link-85 MHz, +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link-85 MHz General Description The DS90C385 transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in par- allel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted ...

Page 2

... I Output TRI-STATE ® Current OZ TRANSMITTER SUPPLY CURRENT ICCTW Transmitter Supply Current Worst Case DS90C385 ICCTG Transmitter Supply Current 16 Grayscale DS90C385 ICCTW Transmitter Supply Current Worst Case DS90C365 www.national.com (Note 1) Package Derating: DS90C365 ESD Rating (HBM, 1.5k , 100pF) (EIAJ 200 pF) −0.3V to +4V Latch Up Tolerance + 0 ...

Page 3

Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter TRANSMITTER SUPPLY CURRENT ICCTG Transmitter Supply Current 16 Grayscale DS90C365 ICCTZ Transmitter Supply Current Power Down Note 1: “Absolute Maximum Ratings” are those values beyond which ...

Page 4

Transmitter Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol TPPos0 Transmitter Output Pulse Position for Bit 0 (Figures 13, 14) (Note 5) TPPos1 Transmitter Output Pulse Position for Bit 1 TPPos2 Transmitter Output Pulse Position ...

Page 5

... AC Timing Diagrams (Continued) FIGURE 2. “16 Grayscale” Test Pattern - DS90C385 (Notes 8, 9, 10) DS100868-5 5 www.national.com ...

Page 6

... Note 9: Figures show a falling edge data strobe (TxCLK IN/RxCLK OUT). Note 10: Recommended pin to signal mapping. Customer may choose to define differently. FIGURE 4. DS90C385/DS90C365 (Transmitter) LVDS Output Load FIGURE 5. DS90C385/DS90C365 (Transmitter) LVDS Transition Times FIGURE 6. DS90C385/DS90C365 (Transmitter) Input Clock Transition Time www.national.com DS100868-31 DS100868-30 ...

Page 7

... AC Timing Diagrams (Continued) FIGURE 7. DS90C385/DS90C365 (Transmitter) Setup/Hold and High/Low Times (Falling Edge Strobe) FIGURE 8. DS90C385/DS90C365 (Transmitter) Clock In to Clock Out Delay FIGURE 9. DS90C385/DS90C365 (Transmitter) Phase Lock Loop Set Time DS100868-10 DS100868-12 DS100868-14 7 www.national.com ...

Page 8

... AC Timing Diagrams (Continued) FIGURE 10. 28 Parallel TTL Data Inputs Mapped to LVDS Outputs - DS90C385 FIGURE 11. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs - DS90C365 www.national.com FIGURE 12. Transmitter Power Down Delay 8 DS100868-17 DS100868-32 DS100868-18 ...

Page 9

... AC Timing Diagrams (Continued) FIGURE 13. Transmitter LVDS Output Pulse Position Measurement - DS90C385 9 DS100868-26 www.national.com ...

Page 10

... AC Timing Diagrams (Continued) FIGURE 14. Transmitter LVDS Output Pulse Position Measurement - DS90C365 FIGURE 15. TJCC Test Setup - DS90C385 Shown www.national.com 10 DS100868-33 DS100868-27 ...

Page 11

... AC Timing Diagrams (Continued) FIGURE 16. Timing Diagram of the Input cycle-to-cycle clock jitter DS90C385 Pin Description — FPD Link Transmitter Pin Name I/O No. TxIN I 28 TTL level input. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines — FPLINE, FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable). ...

Page 12

... The DS90C385/DS90C365 transmitter input and control inputs accept 3.3V TTL/CMOS levels. They are not 5V tolerant implement a falling edge device for the DS90C385/ DS90C365, the R_FB pin may be tied to ground OR left unconnected (an internal pull-down resistor biases this pin low). Biasing this pin to Vcc implements a rising edge device. peated at a period of 2µ ...

Page 13

... Pin Diagram DS90C385 DS100868-23 Truth Table TABLE 1. Programmable Transmitter (DS90C385/DS90C365) Pin R_FB R_FB DS90C365 Application Condition Strobe Status R_FB = V Rising edge strobe CC R_FB = GND or NC Falling edge strobe 13 DS100868-24 DS100868-3 www.national.com ...

Page 14

14 ...

Page 15

... Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Molded Thin Shrink Small Outline Package, JEDEC Dimensions in millimeters only Order Number DS90C385MTD NS Package Number MTD56 15 www.national.com ...

Page 16

... National Semiconductor Asia Pacific Customer Fax: +49 (0) 1 80-530 85 86 Response Group Email: europe.support@nsc.com Tel: 65-2544466 Fax: 65-2504466 Tel: +49 (0) 1 80-532 78 32 Email: sea.support@nsc.com Tel: +49 (0) 1 80-534 16 80 National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 ...

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