DS90C385 National Semiconductor, DS90C385 Datasheet - Page 12

• Manufacturer Part Number: DS90C385
• Description: +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-85 MHz/ +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) L
• Manufacturer: National Semiconductor

www.national.com
PWR DOWN
V
GND
PLL V
PLL GND
LVDS V
LVDS GND
DS90C365 Pin Description — FPD Link Transmitter
Applications Information
The DS90C385/DS90C365 are backward compatible with
the DS90C383/DS90C363, DS90C383A/DS90C363A and
are a pin-for-pin replacement. The device (DS90C385/
DS90C365) utilizes a different PLL architecture employing
an internal 7X clock for enhanced pulse position control.
This device (DS90C385/DS90C365) also features reduced
variation of the TCCD parameter which is important for dual
pixel applications. (See AN-1084) TCCD variation has been
measured to be less than 500ps at 85MHz under normal op-
erating conditions.
This device may also be used as a replacement for the
DS90CF583/563 (5V, 65MHz) and DS90CF581/561 (5V,
40MHz) FPD-Link Transmitters with certain considerations/
modifications:
Transmitter Clock Jitter Cycle-to-Cycle
Figures 15 and 16 illustrate the timing of the input clock rela-
tive to the input data. The input clock (TxCLKin) is intention-
ally shifted to the left −3ns and +3ns to the right when data
(Txin0-27) is high. This 3ns of cycle-to-cycle clock jitter is re-
CC
Pin Name
CC
CC
I/O
I
I
I
I
I
I
I
No.
1
3
4
1
2
1
3
TTL level input. When asserted (low input) TRI-STATES the outputs, ensuring low current at
power down.
Power supply pins for TTL inputs.
Ground pins for TTL inputs.
Power supply pin for PLL.
Ground pins for PLL.
Power supply pin for LVDS outputs.
Ground pins for LVDS outputs.
12
1. Change 5V power supply to 3.3V. Provide this supply to
2. The DS90C385/DS90C365 transmitter input and control
3. To implement a falling edge device for the DS90C385/
peated at a period of 2µs, which is the period of the input
data (1µs high, 1µs low). At different operating frequencies
the N Cycle is changed to maintain the desired 3ns cycle-to-
cycle jitter at 2µs period.
the V
inputs accept 3.3V TTL/CMOS levels. They are not 5V
tolerant.
DS90C365, the R_FB pin may be tied to ground OR left
unconnected (an internal pull-down resistor biases this
pin low). Biasing this pin to Vcc implements a rising edge
device.
Description
CC
, LVDS V
(Continued)
CC
and PLL V
CC
of the transmitter.