DS90C385 National Semiconductor, DS90C385 Datasheet - Page 11

• Manufacturer Part Number: DS90C385
• Description: +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-85 MHz/ +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) L
• Manufacturer: National Semiconductor

TxIN
TxOUT+
TxOUT−
FPSHIFT IN
R_FB
TxCLK OUT+
TxCLK OUT−
PWR DOWN
V
GND
PLL V
PLL GND
LVDS V
LVDS GND
TxIN
TxOUT+
TxOUT−
FPSHIFT IN
R_FB
TxCLK OUT+
TxCLK OUT−
AC Timing Diagrams
DS90C385 Pin Description — FPD Link Transmitter
DS90C365 Pin Description — FPD Link Transmitter
CC
Pin Name
Pin Name
CC
CC
I/O
I/O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
No.
No.
28
21
4
4
1
1
1
1
1
3
4
1
2
1
3
3
3
1
1
1
1
FIGURE 16. Timing Diagram of the Input cycle-to-cycle clock jitter
TTL level input. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines — FPLINE,
FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable).
Positive LVDS differentiaI data output.
Negative LVDS differential data output.
TTL Ievel clock input. Pin name TxCLK IN.
Programmable strobe select (See Table 1).
Positive LVDS differential clock output.
Negative LVDS differential clock output.
TTL level input. When asserted (low input) TRI-STATES the outputs, ensuring low current at
power down.
Power supply pins for TTL inputs.
Ground pins for TTL inputs.
Power supply pin for PLL.
Ground pins for PLL.
Power supply pin for LVDS outputs.
Ground pins for LVDS outputs.
TTL level input. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines — FPLINE,
FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable).
Positive LVDS differential data output.
Negative LVDS differential data output.
TTL Ievel clock input. Pin name TxCLK IN.
Programmable strobe select (See Table 1).
Positive LVDS differential clock output.
Negative LVDS differential clock output.
(Continued)
11
Description
Description
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DS100868-28