CA3318CE Intersil, CA3318CE Datasheet - Page 12

• Manufacturer Part Number: CA3318CE
• Description: 8 BIT "FLASH" A/D
• Manufacturer: Intersil

Specifications of CA3318CE

• Rohs Status: RoHS non-compliant
• Other names: CA3318

NOTE: 1. The voltages listed above are the ideal centers of each output code shown as a function of its associated reference voltage.
Reducing Power
Most power is consumed while in the auto-balance state.
When operating at lower than 15MHz clock speed, power
can be reduced by stretching the sample (φ2) time. The con-
straints are a minimum balance time (φ1) of 33ns, and a
maximum sample time of 500ns. Longer sample times cause
droop in the auto-balance capacitors. Power can also be
reduced in the reference string by switching the reference on
only during auto-balance.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reli-
able. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
1
1
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2
2
Full Scale - 1 LSB
DESCRIPTION
Full Scale + 1 LSB
Full Scale - 1 LSB
1
1
3
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Over Flow
4
2
4
Full Scale
CODE
Full Scale
Full Scale
Full Scale
1 LSB
2 LSB
Zero
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6.40V (V)
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INPUT VOLTAGE
V
0.025
3.175
3.225
6.375
0.00
0.05
1.60
3.20
4.80
6.35
6.40
REF
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(NOTE 1)
5.12V (V)
V
0.00
0.02
0.04
1.28
2.54
2.56
2.58
3.84
5.08
5.10
5.12
REF
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TABLE 1. OUTPUT CODE TABLE
OF
0
0
0
0
0
0
0
0
0
0
1
MSB
B8
0
0
0
0
0
1
1
1
1
1
1
CA3318
12
B7
0
0
0
1
1
0
0
1
1
1
1
Clock Input
The Clock and Phase inputs feed buffers referenced to
V
potentials, while the clock (if DC coupled) should be driven
at least from 0.2 to 0.7 x (V
be AC coupled with at least a 1V
drive levels or 5V QMOS levels when V
5V.
AA
BINARY OUTPUT CODE
+ and V
B6
0
0
0
0
1
0
0
0
1
1
1
AA
B5
0
0
0
0
1
0
0
0
1
1
1
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-. Phase should be tied to one of these two
B4
0
0
0
0
1
0
0
0
1
1
1
AA
B3
0
0
0
0
1
0
0
0
1
1
1
+ - V
P-P
AA
B2
0
0
1
0
1
0
0
0
1
1
1
swing. This allows TTL
-). The clock may also
AA
LSB
B1
+ is greater than
0
1
0
0
1
0
1
0
0
1
1
DECIMAL
COUNT
127
128
129
192
254
255
511
64
0
1
2
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