CA3318CE Intersil, CA3318CE Datasheet

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CA3318CE

Manufacturer Part Number
CA3318CE
Description
8 BIT "FLASH" A/D
Manufacturer
Intersil
Datasheet

Specifications of CA3318CE

Rohs Status
RoHS non-compliant
Other names
CA3318
November 2002
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Features
• CMOS Low Power with SOS Speed (Typ) . . . . . . . .150mW
• Parallel Conversion Technique
• 15MHz Sampling Rate (Conversion Time) . . . . . . . 67ns
• 8-Bit Latched Three-State Output with Overflow Bit
• Accuracy (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . . ±1 LSB
• Single Supply Voltage . . . . . . . . . . . . . . . . . . 4V to 7.5V
• 2 Units in Series Allow 9-Bit Output
• 2 Units in Parallel Allow 30MHz Sampling Rate
Applications
• TV Video Digitizing (Industrial/Security/Broadcast)
• High Speed A/D Conversion
• Ultrasound Signature Analysis
• Transient Signal Analysis
• High Energy Physics Research
• General-Purpose Hybrid ADCs
• Optical Character Recognition
• Radar Pulse Analysis
• Motion Signature Analysis
• µP Data Acquisition Systems
Part Number Information
Pinout
CA3318CE
CA3318CM
CA3318CD
PART NUMBER LINEARITY (INL, DNL)
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
±1.5 LSB
±1.5 LSB
±1.5 LSB
®
(DIG. SUP.) V
(DIG. GND) V
OVERFLOW
(MSB) B8
(LSB) B1
SAMPLING RATE
15MHz (67ns)
15MHz (67ns)
15MHz (67ns)
1
/
B2
B3
B4
B5
B6
B7
4
SS
DD
R
10
11
12
1
2
3
4
5
6
7
8
9
(PDIP, SBDIP, SOIC)
TOP VIEW
CA3318
1
Description
The CA3318 is a CMOS parallel (FLASH) analog-to-digital
converter designed for applications demanding both low
power consumption and high speed digitization.
The CA3318 operates over a wide full scale input voltage
range of 4V up to 7.5V with maximum power consumption
depending upon the clock frequency selected. When
operated from a 5V supply at a clock frequency of 15MHz,
the typical power consumption of the CA3318 is 150mW.
The intrinsic high conversion rate makes the CA3318 ideally
suited for digitizing high speed signals. The overflow bit
makes possible the connection of two or more CA3318s in
series to increase the resolution of the conversion system. A
series connection of two CA3318s may be used to produce a
9-bit high speed converter. Operation of two CA3318s in
parallel doubles the conversion speed (i.e., increases the
sampling rate from 15MHz to 30MHz).
256 paralleled auto balanced voltage comparators measure
the input voltage with respect to a known reference to
produce the parallel bit outputs in the CA3318.
255 comparators are required to quantize all input voltage
levels in this 8-bit converter, and the additional comparator is
required for the overflow bit.
TEMP. RANGE (
24
23
22
21
20
19
18
17
16
15
14
13
-40 to 85
-40 to 85
-40 to 85
V
3
V
V
p
PHASE
CLK
V
V
V
CE1
CE2
/
AA
REF
IN
AA
IN
REF
4
R
+ (ANA. SUP.)
- (ANA. GND)
+
-
o
C)
8-Bit, Flash A/D Converter
CA3318
24 Ld PDIP
24 Ld SOIC
24 Ld SBDIP
CMOS Video Speed,
PACKAGE
E24.6
M24.3
D24.6
PKG. NO.
FN3103.3

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CA3318CE Summary of contents

Page 1

... Radar Pulse Analysis • Motion Signature Analysis • µP Data Acquisition Systems Part Number Information PART NUMBER LINEARITY (INL, DNL) ±1.5 LSB CA3318CE ±1.5 LSB CA3318CM ±1.5 LSB CA3318CD Pinout CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. ...

Page 2

Functional Block Diagram φ φ φ ANALOG SUPPLY REF / 2Ω REF 7Ω ...

Page 3

Absolute Maximum Ratings DC Supply Voltage Range ( -0. (Referenced Terminal, Whichever is More Negative Input ...

Page 4

Electrical Specifications All Reference Points Adjusted, Unless Otherwise Specified (Continued) PARAMETER DIGITAL INPUTS Low Level Input Voltage CE1, CE2 Phase, CLK High Level Input Voltage CE1, CE2 Phase, CLK Input Leakage ...

Page 5

Timing Waveforms (Continued) CE1 CE2 t DIS BITS DATA OF AUTO BALANCE CLOCK NO MAX LIMIT DATA FIGURE 3A. STANDBY IN INDEFINITE AUTO BALANCE (SHOWN WITH PHASE = LOW) SAMPLE CLOCK N 500ns MAX DATA FIGURE 3B. ...

Page 6

Typical Performance Curves (MHz) S FIGURE 4. DEVICE CURRENT vs SAMPLE FREQUENCY 8 15MHz 1MHz S I 7.8 7.6 7.4 7.2 7.0 6.8 6.6 6.4 6.2 ...

Page 7

Typical Performance Curves 8.0 7.6 7.2 6.8 6.4 6.0 5.6 5.2 4.8 4.4 4.0 Pin Descriptions PIN NAME DESCRIPTION 1 B1 Bit 1 (LSB Bit Bit Bit Bit 5 ...

Page 8

At the same time a second set of commutating capacitors and amplifiers is also auto-balanced. The balancing of the second-stage amplifier at its intrinsic trip point removes any tracking differences between the first and second amplifier stages. The cascaded auto-balance ...

Page 9

TO 30V + INPUT 3 18Ω CA3085E (NOTE IOT 10µF, TAN (NOTE) 1.5K NOTE: Bypass analog GND near A/D with 0.1µF ceramic REF cap. Parts noted should have low ...

Page 10

Signal-to-Noise + Distortion Ratio (SINAD) SINAD is the measured RMS signal to RMS sum of all other spectral components below the Nyquist frequency excluding DC. Effective Number of Bits (ENOB) The effective number of bits (ENOB) is derived from the ...

Page 11

TANTALUM A +4V TO +6.5V REFERENCE OPTIONAL CAP (SEE TEXT) 0.01µF CLOCK SOURCE INPUT SIGNAL AMPLIFIER/BUFFER (SEE TEXT) FIGURE 14. TYPICAL CIRCUIT CONFIGURATION FOR THE CA3318 WITH NO LINEARITY ADJUST AMP SIGNAL SOURCE SIGNAL GROUND - + ANALOG SUPPLIES ...

Page 12

... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reli- able. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...

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