CA3306CE Intersil, CA3306CE Datasheet

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CA3306CE

Manufacturer Part Number
CA3306CE
Description
IC CONV A/D FLASH 6BIT 18-DIP
Manufacturer
Intersil
Datasheet

Specifications of CA3306CE

Rohs Status
RoHS non-compliant
Other names
CA3306

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November 2002
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Features
• CMOS Low Power with Video Speed (Typ) . . . . . 70mW
• Parallel Conversion Technique
• Signal Power Supply Voltage . . . . . . . . . . . 3V to 7.5V
• 15MHz Sampling Rate with Single 5V Supply
• 6-Bit Latched Three-State Output with Overflow Bit
• Pin-for-Pin Retrofit for the CA3300
Applications
• TV Video Digitizing
• Ultrasound Signature Analysis
• Transient Signal Analysis
• High Energy Physics Research
• High Speed Oscilloscope Storage/Display
• General Purpose Hybrid ADCs
• Optical Character Recognition
• Radar Pulse Analysis
• Motion Signature Analysis
• Robot Vision
Part Number Information
Pinouts
CA3306E
CA3306CE
CA3306M
CA3306CM
CA3306D
CA3306CD
CA3306J3
CA3306J3
PART NUMBER LINEARITY (INL, DNL)
OVERFLOW
(MSB) B6
PHASE
V
REF
CLK
CE2
CE2
V
CA3306 (PDIP, SBDIP)
V
SS
Z
+
1
2
3
4
5
6
7
8
9
TOP VIEW
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
±0.5 LSB
±0.5 LSB
±0.5 LSB
±0.5 LSB
±0.5 LSB
±0.5 LSB
±0.5 LSB
±0.5 LSB
®
18
17
16
15
14
13
12
11
10
B5
B4
REF
CENTER
B3
B2
B1 (LSB)
V
V
V
DD
IN
REF
-
SAMPLING RATE
10MHz (100ns)
10MHz (100ns)
10MHz (100ns)
10MHz (100ns)
15MHz (67ns)
15MHz (67ns)
15MHz (67ns)
15MHz (67ns)
OVERFLOW
(MSB) B6
PHASE
V
REF
CLK
CE2
CE1
V
NC
V
SS
Z
+
10
CA3306 (SOIC)
1
2
3
4
5
6
7
8
9
TOP VIEW
1
Description
The CA3306 family are CMOS parallel (FLASH) analog-to-digital
converters designed for applications demanding both low power
consumption and high speed digitization. Digitizing at 15MHz, for
example, requires only about 50mW.
The CA3306 family operates over a wide, full scale signal input volt-
age range of 1V up to the supply voltage. Power consumption is as
low as 15mW, depending upon the clock frequency selected. The
CA3306 types may be directly retrofitted into CA3300 sockets, offer-
ing improved linearity at a lower reference voltage and high operat-
ing speed with a 5V supply.
The intrinsic high conversion rate makes the CA3306 types ideally
suited for digitizing high speed signals. The overflow bit makes pos-
sible the connection of two or more CA3306s in series to increase
the resolution of the conversion system. A series connection of two
CA3306s may be used to produce a 7-bit high speed converter.
Operation of two CA3306s in parallel doubles the conversion speed
(i.e., increases the sampling rate from 15MHz to 30MHz).
Sixty-four paralleled auto balanced comparators measure the input
voltage with respect to a known reference to produce the parallel bit
outputs in the CA3306. Sixty-three comparators are required to
quantize all input voltage levels in this 6-bit converter, and the addi-
tional comparator is required for the overflow bit.
TEMP. RANGE (
20
19
18
17
16
15
14
13
12
11
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-40 to 85
-40 to 85
-40 to 85
-40 to 85
B5
B4
REF
CENTER
B3
B2
B1 (LSB)
V
NC
V
V
DD
IN
REF
CA3306, CA3306A,
-
o
C)
CE2
CE1
18 Ld PDIP
18 Ld PDIP
20 Ld SOIC
20 Ld SOIC
18 Ld SBDIP
18 Ld SBDIP
20 Ld CLCC
20 Ld CLCC
V
NC
V
SS
Flash A/D Converters
Z
PACKAGE
4
5
6
7
8
3
9 10 11 12 13
CA3306 (CLCC)
2
TOP VIEW
CA3306C
6-Bit, 15 MSPS,
1 20 19
E18.3
E18.3
M20.3
M20.3
D18.3
D18.3
J20.B
J20.B
18
17
16
15
14
PKG. NO.
FN3102.2
REF
CENTER
B3
B2
B1 (LSB)
V
DD

Related parts for CA3306CE

CA3306CE Summary of contents

Page 1

... Optical Character Recognition • Radar Pulse Analysis • Motion Signature Analysis • Robot Vision Part Number Information PART NUMBER LINEARITY (INL, DNL) ±0.5 LSB CA3306E ±0.5 LSB CA3306CE ±0.5 LSB CA3306M ±0.5 LSB CA3306CM ±0.5 LSB CA3306D ±0.5 LSB CA3306CD ± ...

Page 2

Functional Block Diagram V IN φ 1 R/2 φ REF ≅ 120Ω R REF CENTER REF R/2 ≅ 50kΩ CLOCK PHASE ZENER 6.2V NOMINAL DIODE V SS Typical Application Circuit ...

Page 3

Absolute Maximum Ratings DC Supply Voltage Range Voltage Referenced to V Terminal . . . . . . . . . . . -0.5V to +8.5V SS Input Voltage Range All Inputs Except Zener ...

Page 4

Electrical Specifications CA3306A, 10MHz for CA3306C (Continued) PARAMETER ANALOG INPUTS Positive Full Scale Input Range Negative Full Scale Input Range Input Capacitance Input Current INTERNAL VOLTAGE REFERENCE Zener Voltage Zener Dynamic Impedance Zener Temperature Coefficient ...

Page 5

Timing Waveforms COMPARATOR DATA IS LATCHED CLOCK IF PHASE IS HIGH CLOCK IF PHASE IS LOW DATA CE1 CE2 t DIS BITS 1-6 DATA OF CA3306, CA3306A, CA3306C DECODED DATA IS SHIFTED TO OUTPUT REGISTERS φ φ ...

Page 6

Timing Waveforms SAMPLE ENDS φ 1 φ CLOCK 2 t OLD DATA OUTPUT FIGURE 3A. φ CLOCK 2 OLD DATA OUTPUT Typical Performance Curves REF ...

Page 7

Typical Performance Curves 0. 4.8V A REF 0.30 DD 0.25 INTEGRAL 0.20 0.15 DIFFERENTIAL 0.10 0.05 0 0.1 1 CLOCK FREQUENCY (MHz) FIGURE 6. TYPICAL NON-LINEARITY AS A FUNCTION OF ...

Page 8

Typical Performance Curves REF SINE WAVE REF CLK/2 30 DECODER 25 LIMITED ...

Page 9

Typical Performance Curves 6.00 5.70 5.40 5.10 4.80 4.50 4.20 3.90 3.60 3.30 3.00 0.00 Pin Descriptions PIN NUMBER DIP SOIC NAME CE2 6 ...

Page 10

CE1 Don’t care (NOTE 1) INPUT VOLTAGE V V REF REF 6.40 5.12 CODE DESCRIPTION (V) (V) Zero 0.00 0.00 1 LSB 0.10 0.08 2 LSB 0.20 0.16 • • • • Full ...

Page 11

Device Operation A sequential parallel technique is used by the CA3306 converter to obtain its high speed operation. The sequence consists of the “Auto Balance” phase φ1 and the “Sample Unknown” phase φ2. (Refer to the circuit diagram.) Each conversion ...

Page 12

The CA3306 outputs a short (less than 10ns) current spike several mA amplitude (See Typical Performance Curves) at the beginning of the sample phase. (To a lesser extent, a spike also appears at the beginning of auto ...

Page 13

... RMS value of the measured input signal. Operating and Handling Considerations HANDLING All inputs and outputs of Intersil CMOS devices have a network for electrostatic protection during handling. Recom- mended handling practices for CMOS devices are described in AN6525. “Guide to Better Handling and Operation of CMOS Integrated Circuits.” ...

Page 14

Application Circuits V+ 1K CLOCK INPUT 0.1µF ADJUST POT 0.1µF FIGURE 17. TYPICAL CA3306 7-BIT RESOLUTION CONFIGURATION CA3306, CA3306A, CA3306C 0.1µ CA3306 ...

Page 15

Application Circuits (Continued) V+ CLOCK INPUT 0.1µF ADJUST POT 0.1µF FIGURE 18. TYPICAL CA3306 6-BIT RESOLUTION CONFIGURATION WITH DOUBLE SAMPLING RATE CAPABILITY CA3306, CA3306A, CA3306C ...

Page 16

Application Circuits (Continued) S/ ∑ FIGURE 19. TYPICAL CA3306, 800ns, 12-BIT ADC SYSTEM B6’ NO. 1 6-BIT FLASH B1’ ADC 6-BIT DAC (12 BIT ACCURACY) X32 B6 NO. 2 6-BIT FLASH B1 ADC B7 NO. 3 ...

Page 17

... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...

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