ca3306 Intersil Corporation, ca3306 Datasheet
ca3306
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ca3306 Summary of contents
Page 1
... The intrinsic high conversion rate makes the CA3306 types ideally suited for digitizing high speed signals. The overflow bit makes pos- sible the connection of two or more CA3306s in series to increase the resolution of the conversion system. A series connection of two CA3306s may be used to produce a 7-bit high speed converter. ...
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... REF CENTER REF R/2 50k CLOCK PHASE ZENER 6.2V NOMINAL DIODE V SS Typical Application Circuit 560 +12V CLOCK +12V CA741CE CA3306, CA3306A, CA3306C 1 1 COMP 64 COMP 63 COMPARATOR COMP LATCHES 32 AND ENCODER LOGIC COMP 2 COMP 1 2 (SAMPLE UNKNOWN) 1 (AUTO BALANCE CA3306 ...
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... Maximum Storage Temperature Range . . . . . . . . . .-65 Maximum Lead Temperature (Soldering 10s 300 (SOIC - Lead Tips Only 125 5V 4.8V GND, Clock = 15MHz Square Wave for CA3306 or DD REF SS REF TEST CONDITIONS (Note Minimum (Note 15MHz 100kHz ...
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... OUT V = 4.6V OUT V = 0.4V OUT (Note 4) (Note 4) Continuous Conversion (Note 4) Continuous 1 to overflow output code transition and ( and V -, may be in the range REF REF 4- GND, Clock = 15MHz Square Wave for CA3306 or MIN TYP MAX 1 4 0 500 5 ...
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... CLOCK IF PHASE IS LOW DATA CE1 CE2 t DIS DATA BITS 1-6 OF SAMPLE ENDS 1 CLOCK 2 OLD DATA OUTPUT FIGURE 3A. CLOCK OUTPUT CA3306, CA3306A, CA3306C DECODED DATA IS SHIFTED TO OUTPUT REGISTERS AUTO SAMPLE BALANCE DATA FIGURE 1. INPUT-TO-OUTPUT DIS ...
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... -10 - INPUT VOLTAGE (V) FIGURE 8. TYPICAL PEAK INPUT CURRENT AS A FUNCTION OF INPUT VOLTAGE CA3306, CA3306A, CA3306C 125 100 TEMPERATURE - PLASTIC REF ZENER NOT CONNECTED FIGURE 5. TYPICAL MAXIMUM AMBIENT TEMPERATURE FUNCTION OF SUPPLY VOLTAGE ...
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... FIGURE 10. TYPICAL MAXIMUM CLOCK FREQUENCY AS A FUNCTION OF SUPPLY VOLTAGE 32.5 30.0 27.5 25.0 22.5 20.0 17.5 15.0 -50 - TEMPERATURE ( FIGURE 12. DATA DELAY vs TEMPERATURE 14.0 12.6 11.2 9.8 8.4 7.0 5.6 4.2 2.8 1.4 0.0 -40 -30 -20 - TEMPERATURE ( FIGURE 14 TEMPERATURE DD CA3306, CA3306A, CA3306C (Continued DISSIPATION LIMITED FIGURE 11. DEVICE CURRENT vs SAMPLE FREQUENCY 6 5.7 5.4 5.1 4.8 4.5 4.2 3.9 3.6 3.3 3 100 - ...
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... REF(CTR CA3306, CA3306A, CA3306C (Continued 15MHz S 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 f (MHz) I FIGURE 16. ENOB vs INPUT FREQUENCY Bit 6, Output (MSB). Overflow, Output. Digital Ground. Zener Reference Output. Three-State Output Enable Input, Active Low. See Table 1. ...
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... Full Scale - 1 LSB 6.20 4.96 Full Scale 6.30 5.04 Overflow 6.40 5.12 NOTE: 1. The voltages listed above are the ideal centers of each output code shown as a function of its associated reference voltage. CA3306, CA3306A, CA3306C TABLE 1. CHIP ENABLE TRUTH TABLE CE2 Valid 1 Three-State 0 Three-State TABLE 2. OUTPUT CODE TABLE ...
Page 10
... Valid data now appears two full clock cycles after starting the conversion process. Analog Input Considerations The CA3306 input terminal is characterized by a small capacitance (see Specifications) and a small voltage- dependent current (See Typical Performance Curves). The signal-source impedance should be kept low, however, when operating the CA3306 at high clock rates ...
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... A locally terminated source is generally suffi- cient to drive the CA3306. If gain is required, a high speed, fast settling operational amplifier, such as the HA-5033, HA-2542, or HA5020 is recommended. Digital Input And Output Interfacing The two chip-enable and the phase-control inputs are stan- dard CMOS units ...
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... The first converter can be offset-biased by adding a 20 resistor at the bottom of the ladder and increasing the refer- ence voltage by 1 LSB 6.4V reference is used in the sys- tem, for example, then the first CA3306 will require a 6.5V reference. Definitions Dynamic Performance Definitions Fast Fourier Transform (FFT) techniques are used to evaluate the dynamic performance of the converter ...
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... Application Circuits V+ 1K CLOCK INPUT 0.1 F ADJUST POT 0.1 F FIGURE 17. TYPICAL CA3306 7-BIT RESOLUTION CONFIGURATION CA3306, CA3306A, CA3306C 0 CA3306 CE2 CE1 CLK DD VSS 0 REF REF CA3306 ...
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... Application Circuits (Continued) V+ CLOCK INPUT 0.1 F ADJUST POT 0.1 F FIGURE 18. TYPICAL CA3306 6-BIT RESOLUTION CONFIGURATION WITH DOUBLE SAMPLING RATE CAPABILITY CA3306, CA3306A, CA3306C 0.1 F CA3306 CE2 CE1 CLK DD VSS 0 ...
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... Application Circuits (Continued) S/ FIGURE 19. TYPICAL CA3306, 800ns, 12-BIT ADC SYSTEM CA3306 INPUTS TYPICAL FOR: PHASE CE1 CE2 7406 OPEN COLLECTOR DRIVER CA3306 OUTPUTS TYPICAL FOR: CA3306 FIGURE 20. 5V LOGIC INTERFACE CIRCUIT FOR V CA3306, CA3306A, CA3306C B6’ ...
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... For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 CA3306, CA3306A, CA3306C EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ...