SW006015 Microchip Technology, SW006015 Datasheet - Page 73

• Manufacturer Part Number: SW006015
• Description: C COMPILER MPLAB C32
• Manufacturer: Microchip Technology
• Type: Compilerr
• Series: PIC32r

Specifications of SW006015

• Supported Families: PIC32MX5, MX6, And MX7
• Core Architecture: PIC
• Kit Contents: Software And Docs
• Mcu Supported Families: PIC32 MCUs
• Tool Function: Compiler
• Supported Devices: PIC32 MCUs
• Tool Type: Compiler
• Processor Series: PIC32
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• For Use With/related Products: PIC32
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Compiler Runtime Environment
5.7.2.9.11 Processor Identification Register (PRid – CP0 Register 15, Select 0)
This register is a 32-bit read-only register that contains information identifying the
manufacturer, manufacturer options, processor identification, and revision level of the
processor.
No initialization is performed on this register in the PIC32MX startup code.
5.7.2.9.12 Exception Base Register (EBase – CP0 Register 15, Select 1)
This register is a read/write register containing the base address of the exception
vectors used when Status
equals 0, and a read-only CPU number value that may
BEV
be used by software to distinguish different processors in a multi-processor system.
The EBase register provides the ability for software to identify the specific processor
within a multi-processor system, and allows the exception vectors for each processor
to be different, especially in systems composed of heterogeneous processors. Bits
31..12 of the EBase register are concatenated with zeros to form the base of the
exception vectors when Status
is 0. The exception vector base address comes
BEV
from fixed defaults when Status
is 1, or for any EJTAG Debug exception. The reset
BEV
state of bits 31..12 of the EBase register initialize the exception base register to
16#80000000, providing backward compatibility with Release 1 implementations. Bits
31..30 of the EBase register are fixed with the value 2#10 to force the exception base
address to be in KSEG0 or KSEG1 unmapped virtual address segments.
If the value of the exception base register is to be changed, this must be done with
equal 1. The operation of the processor is UNDEFINED if the Exception
Status
BEV
Base field is written with a different value when Status
is 0.
BEV
Combining bits 31..30 with the Exception Base field allows the base address of the
exception vectors to be placed at any 4K byte page boundary. If vectored interrupts are
used, a vector offset greater than 4K byte can be generated. In this case, bit 12 of the
Exception Base field must be zero. The operation of the processor is UNDEFINED if
software writes bit 12 of the Exception Base field with a 1 and enables the use of a
vectored interrupt whose offset is greater than 4K bytes from the exception base
address.
This register us initialized with the value of the _ebase_address symbol by the
PIC32MX startup code. _ebase_address is provided by the linker script with a
default value of the start of KSEG1 program memory. The user can change this value
by providing the command line option -–defsym _ebase_address=A to the linker.
5.7.2.9.13 Config Register (Config – CP0 Register 16, Select 0)
This register specifies various configuration and capabilities information. Most of the
fields in the Config register are initialized by hardware during the Reset exception
process, or are constant.
No initialization is performed on this register in the PIC32MX startup code.
5.7.2.9.14 Config1 Register (Config1 – CP0 Register 16, Select 1)
This register is an adjunct to the Config register and encodes additional information
about the capabilities present on the core. All fields in the Config1 register are
read-only.
No initialization is performed on this register in the PIC32MX startup code.
5.7.2.9.15 Config2 Register (Config2 – CP0 Register 16, Select 2)
This register is an adjunct to the Config register and is reserved to encode additional
capabilities information. Config2 is allocated for showing the configuration of level 2/3
caches. These fields are reset to 0 because L2/L3 caches are not supported on the
core. All fields in the Config2 register are read-only.
No initialization is performed on this register in the PIC32MX startup code.
© 2007 Microchip Technology Inc.
DS51686A-page 69