SW006015 Microchip Technology, SW006015 Datasheet - Page 72

• Manufacturer Part Number: SW006015
• Description: C COMPILER MPLAB C32
• Manufacturer: Microchip Technology
• Type: Compilerr
• Series: PIC32r

Specifications of SW006015

• Supported Families: PIC32MX5, MX6, And MX7
• Core Architecture: PIC
• Kit Contents: Software And Docs
• Mcu Supported Families: PIC32 MCUs
• Tool Function: Compiler
• Supported Devices: PIC32 MCUs
• Tool Type: Compiler
• Processor Series: PIC32
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• For Use With/related Products: PIC32
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DS51686A-page 68
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5.7.2.9.6
This register controls the expanded interrupt capability added in Release 2 of the
Architecture, including vectored interrupts and support for an external interrupt
controller.
This register contains the vector spacing for interrupt handling. The vector spacing
portion of this register (bits 9..5) is initialized with the value of the _vector_spacing
symbol by the PIC32MX startup code. All other bits are set to 1.
5.7.2.9.7
This register controls the operation of the GPR shadow sets in the processor.
No initialization is performed on this register in the PIC32MX startup code.
5.7.2.9.8
This register contains eight 4-bit fields that provide the mapping from a vector number
to the shadow set number to use when servicing such an interrupt. The values from this
register are not used for a non-interrupt exception, or a non-vectored interrupt
(Cause
SRSCtl
are UNPREDICTABLE. The operation of the processor is UNDEFINED if a value is
written to any field in this register that is greater than the value of SRSCtl
SRSMap register contains the shadow register set numbers for vector numbers 7..0.
The same shadow set number can be established for multiple interrupt vectors,
creating a many-to-one mapping from a vector to a single shadow register set number.
No initialization is performed on this register in the PIC32MX startup code.
5.7.2.9.9
This register primarily describes the cause of the most recent exception. In addition,
fields also control software interrupt requests and the vector through which interrupts
are dispatched. With the exception of the DC, IV, and IP1..IP0 fields, all fields in the
Cause register are read-only. Release 2 of the Architecture added optional support for
an External Interrupt Controller (EIC) interrupt mode, in which IP7..IP2 are
interpreted as the Requested Interrupt Priority Level (RIPL).
The following settings are initialized by the PIC32MX startup code:
• Enable counting of Count register (DC = no change)
• Use the special exception vector (16#200) (IV = 1)
• Disable software interrupt requests (IP1..IP0 = 0)
5.7.2.9.10 Exception Program Counter (EPC – CP0 Register 14, Select 0)
This register is a read/write register that contains the address at which processing
resumes after an exception has been serviced. All bits of the EPC register are
significant and must be writable. For synchronous (precise) exceptions, the EPC
contains one of the following:
• The virtual address of the instruction that was the direct cause of the exception
• The virtual address of the immediately preceding branch or jump instruction, when
On new exceptions, the processor does not write to the EPC register when the EXL bit
in the Status register is set, however, the register can still be written via the MTC0
instruction.
No initialization is performed on this register in the PIC32MX startup code.
the exception causing instruction is a branch delay slot and the Branch Delay
bit in the Cause register is set.
IV
ESS
= 0 or IntCtl
. If SRSCtl
Interrupt Control Register (IntCtl – CP0 Register 12, Select 1)
Shadow Register Control Register (SRSCtl – CP0 Register 12, Select 2)
Shadow Register Map Register (SRSMap – CP0 Register 12, Select 3)
Cause Register (Cause – CP0 Register 13, Select 0)
HSS
VS
is zero, the results of a software read or write of this register
= 0). In such cases, the shadow set number comes from
© 2007 Microchip Technology Inc.
HSS
. The