HW-V2PRO-XLVDS Xilinx Inc, HW-V2PRO-XLVDS Datasheet - Page 3
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HW-V2PRO-XLVDS
Manufacturer Part Number
HW-V2PRO-XLVDS
Description
EVAL BOARD VIRTEX II PRO XLVDS
Manufacturer
Xilinx Inc
Series
Virtex™-II Pror
Type
LVDS Data Transmissionr
Datasheet
1.XC2VP20-5FGG676C.pdf
(430 pages)
Specifications of HW-V2PRO-XLVDS
Contents
Board, Cables, 4 Clock Source Boards and CD
For Use With/related Products
XC2VP20
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
- Current page: 3 of 430
- Download datasheet (4Mb)
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RocketIO Transceiver Features (All Except XC2VPX20 and XC2VPX70)
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PowerPC RISC Processor Block Features (All Except XC2VP2)
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Virtex-II Pro Platform FPGA Technology (All Devices)
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1. Refer to
DS083 (v4.7) November 5, 2007
Product Specification
Programmable Receiver Equalization
Internal AC Coupling
On-Chip 50Ω Termination
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Pre- and Post-Driver Serial and Parallel TX-to-RX
Full-Duplex Serial Transceiver (SERDES) Capable of
Baud Rates from 600 Mb/s to 3.125 Gb/s
100 Gb/s Duplex Data Rate (20 Channels)
Monolithic Clock Synthesis and Clock Recovery (CDR)
Fibre Channel, 10G Fibre Channel, Gigabit Ethernet,
10 Gb Attachment Unit Interface (XAUI), and
Infiniband-Compliant Transceivers
8-, 16-, or 32-bit Selectable Internal FPGA Interface
8B /10B Encoder and Decoder (optional)
Embedded 300+ MHz Harvard Architecture Block
Low Power Consumption: 0.9 mW/MHz
Five-Stage Data Path Pipeline
Hardware Multiply/Divide Unit
Thirty-Two 32-bit General Purpose Registers
16 KB Two-Way Set-Associative Instruction Cache
16 KB Two-Way Set-Associative Data Cache
SelectRAM+ Memory Hierarchy
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Arithmetic Functions
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Flexible Logic Resources
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High-Performance Clock Management Circuitry
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Eliminates the need for external termination
resistors
Up to 8 Mb of True Dual-Port RAM in 18 Kb block
SelectRAM+ resources
Up to 1,378 Kb of distributed SelectRAM+
resources
High-performance interfaces to external memory
Dedicated 18-bit x 18-bit multiplier blocks
Fast look-ahead carry logic chains
Up to 88,192 internal registers/latches with Clock
Enable
Up to 88,192 look-up tables (LUTs) or cascadable
variable (1 to 16 bits) shift registers
Wide multiplexers and wide-input function support
Horizontal cascade chain and Sum-of-Products
support
Internal 3-state busing
Up to twelve Digital Clock Manager (DCM) modules
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XAPP653
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Precise clock de-skew
for more information.
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Introduction and Overview
www.xilinx.com
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Internal Loopback Modes for Testing Operability
Programmable Comma Detection
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8B/10B and 64B/66B Encoding Blocks
50Ω /75Ω on-chip Selectable Transmit and Receive
Terminations
Programmable Comma Detection
Channel Bonding Support (from 2 to 20 Channels)
Rate Matching via Insertion/Deletion Characters
Four Levels of Selectable Pre-Emphasis
Five Levels of Output Differential Voltage
Per-Channel Internal Loopback Modes
2.5V Transceiver Supply Voltage
Memory Management Unit (MMU)
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Dedicated On-Chip Memory (OCM) Interface
Supports IBM CoreConnect™ Bus Architecture
Debug and Trace Support
Timer Facilities
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Active Interconnect Technology
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SelectIO™-Ultra Technology
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Allows for any protocol
Allows for detection of any 10-bit character
64-entry unified Translation Look-aside Buffers (TLB)
Variable page sizes (1 KB to 16 MB)
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16 global clock multiplexer buffers in all parts
Fourth-generation segmented routing structure
Fast, predictable routing delay, independent of
fanout
Deep sub-micron noise immunity benefits
Up to 1,164 user I/Os
Twenty-two single-ended standards and
ten differential standards
Programmable LVCMOS sink/source current (2 mA
to 24 mA) per I/O
XCITE Digitally Controlled Impedance (DCI) I/O
PCI/ PCI-X support
Differential signaling
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Flexible frequency synthesis
High-resolution phase shifting
840 Mb/s Low-Voltage Differential Signaling I/O
(LVDS) with current mode drivers
On-chip differential termination
Bus LVDS I/O
(1)
Module 1 of 4
2
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