MPC8360E-MDS-PBE Freescale Semiconductor, MPC8360E-MDS-PBE Datasheet - Page 2

• Manufacturer Part Number: MPC8360E-MDS-PBE
• Description: BOARD PROCESSOR FOR MPC8360E
• Manufacturer: Freescale Semiconductor

Specifications of MPC8360E-MDS-PBE

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Connectivity
The MPC8360E processor is designed to
support a wide range of communications
interfaces, such as MII, RMII, GMII, TBI,
RTBI, NMSI, UTOPIA, POS and TDM.
The dual 32-bit DDR memory controllers
help to ensure high-speed memory
access and a local system bus operating
up to 133 MHz. Additional system
connectivity is supplied by dual UART,
dual inter-integrated circuit (I
peripheral interface (SPI), PCI interfaces
and Universal Serial Bus (USB) interface
(USB 2.0 full/low speed compatible).
Integrated Security
The MPC8360E and MPC8358E
processors feature integrated security
with the powerfully integrated security
engine derived from Freescale’s security
coprocessor product line. Integrated
security supports DES, 3DES, MD-5, SHA-1,
AES and ARC-4 encryption algorithms, as
well as a public key accelerator and an
on-chip random number generator. The
integrated security engine is capable of
single-pass encryption and authentication,
as required by IPsec, the IEEE
standard and other security protocols.
Typical Applications
• DSL infrastructure
• Wireless infrastructure
• Small and medium enterprise (SME) routers
• Add/drop multiplexers and digital
• Integrated voice routers and digital
• Multi-service access nodes (MSAN)
• Industrial and general-purpose
cross connects
IP-based private automatic branch
exchange (PABX)
networking
DSLAMs
MTUs
Base transceiver station (BTS)
Base station controller (BSC)
Radio network controller (RNC)
Node B
Intrusion detection/protection
system (IDS/IPS)
Secure VPN
Firewall
2
C), dual serial
®
802.11i
QUICC Engine
Freescale’s QUICC Engine technology
includes two optimized RISC processors
supporting a wide range of protocols while
providing high data throughput of up to
1.2 Gbps. Flexibility is provided by the
eight unified communications controllers
(UCCs) providing support for Fast Ethernet,
Gigabit Ethernet, high-level data link control
(HDLC) and ATM/POS at up to OC-12
speeds. The MPC8360E and MPC8358E
support connectivity up to eight T1/E1s.
The MPC8360E supports eight TDMs
and the MPC8358E supports four TDMs,
with each TDM capable of supporting a
clear channel T3/E3. One multi-channel
communications controller (MCC) on the
MPC8360E supports up to 256 x 64 kbps
HDLC or transparent channels.
To simplify the transition from current
PowerQUICC designs, the advanced
QUICC Engine technology maintains a
high degree of software compatibility
with previous-generation PowerQUICC
processor-based designs. This helps ease
migration issues, reduce development costs
and speed time to market.
The QUICC Engine technology builds upon
the PowerQUICC shrink-wrapped software
protocol support and provides enhancements
in terms of interworking, parsing, switching
and forwarding. A full set of configurable
driver software and initialization support
will also be available.
Interworking
With the potential to offer three revenue
streams from a single IP packet network,
the triple play of voice, video and data is the
goal of every telecom operator. IP is the key
enabler, and in time, it will be universal. Until
then, equipment has to interoperate between
circuit- and packet-switched networks and
between many standards and protocols.
The interoperability between standard
protocols is referred to as interworking.
The QUICC Engine block supports
ATM-to-Ethernet interworking without
CPU intervention in support of the
industry-standard RFC2684 specification.
In addition, it can support MC/MLPPP to
Ethernet interworking.
It is able to perform powerful table lookup
functions including multiple fields from
Layers 2 to 4 without CPU intervention.
Key Advantages
• High-performance, low-power and
• Advanced QUICC Engine technology
• DDR memory support—one 64-bit or
• Low risk when transitioning from legacy
• Quick to market enabled by
• Low bill of material (BOM) cost
Product Family Highlights
• e300 core, built on Power Architecture
• DDR memory controller, 1 x 32/64-bit or
• QUICC Engine technology with eight
• 32-bit PCI interface
• 32-bit local bus interface
• Optional integrated security
cost-effective communications
processor solution
supporting a wide range of protocols
and associated interworking
2 x 32-bit interfaces
to IP-based systems
software compatibility
technology (enhanced version of the 603e
core with larger caches)
2 x 32-bit, up to 333 MHz
communications interfaces supporting
Fast Ethernet, Gigabit Ethernet, ATM,
POS, HDLC, asynchronous HDLC,
UART and transparent
Convergence for packet-based networks
Compatibility with current PowerQUICC
offerings
Cost-effective solution at the chip
and system level