HSP-EVAL Intersil, HSP-EVAL Datasheet
HSP-EVAL
Specifications of HSP-EVAL
Related parts for HSP-EVAL
HSP-EVAL Summary of contents
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... USER’S MANUAL DSP Evaluation Platform The HSP-EVAL is the mother board for a set of daughter boards based on the HSPxxxxx family of Digital Signal Processing products. Each product specific daughter board is mated with the HSP-EVAL to provide a mechanism for rapid evaluation and prototyping. As shown in Figure 1, the HSP-EVAL consists of a series of busses which provide input, output, and control to the target daughter board ...
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... A simple procedure for assembly and operation of the target daughter board with the HSP-EVAL is described in the respective daughter board’s User’s Manual. What follows in this document is a detailed description of the HSP-EVAL and its operation. Bus Structure The HSP-EVAL utilizes a series of 16-bit busses for daughter board input, output and control as shown in Figure 1 ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 3 HSP-EVAL TABLE 2. PIN ASSIGNMENTS FOR 96 PIN OUTPUT CONNECTOR P2 ROW C ...
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... Parallel Port Bus. Data transfers involving these registers are described in the following sections. The HSP-EVAL has a set of eight 8-bit data registers which are organized as a set of four “logical” input and control registers, Input Registers 1 thru 3 and the CTL Control Register ...
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... HSP- EVAL. The address register specifies the particular register for loading, as well as the board address of the HSP-EVAL targeted for the data download. The HSP-EVAL board address is selected in the J4 Jumper Field (see Confi ...
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... End” status line of the PC's DATA ON OUTPUT parallel port. BUS 1 The HSP-EVAL can be configured such that one of the four Status Bus Lines STAT0-3 is selected for monitoring via the PCRD0-1 lines of the Parallel Port Bus. To select one of the REGISTER ...
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... Daughter Board Output Connector J2 to the HSP-EVAL's 96 Pin Output Connector P2. The on-board oscillator is selected as a clock source by inserting a jumper at the OSC_CLK position in the J4 jumper field. In this mode, the oscillator on-board the HSP-EVAL is supplied as a clock to the daughter board. Since data CTL3 CTL2 ...
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... Intersil or Intersil’s' authorized representatives. JUMPERS Intersil makes no other express or implied warranty with respect to the HSP-EVAL other than the limited warranty set forth above. Intersil disclaims all implied warranties of merchantability and/or fitness for a particular purpose. In any event, all implied warranties shall be limited to the duration of this warranty ...
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OE_BUS2 1 VCC PCD0 2 PCD1 3 Z1 PCD2 4 PCD3 5 PCD4 6 PCD5 7 PCD6 8 R SIP10 PCD7 9 10 OE_BUS3 G2A 5 G2B RNGSEL U6 PCD0 2 ...
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ST U13 CTL1 10 SER OUT1_0 OUT1_1 B STAT[0..3] 13 OUT1_2 C OUT1_3 14 D OUT1_4 3 E OUT1_5 OUT1_6 G OUT1_7 CLK 15 QH INH 7 1 SH/LD ...
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AUXIN1 AUXIN0 CLKOUT VCC P2A P2B 1 1 OUT2_0 2 2 OUT2_2 3 3 OUT2_4 4 4 OUT2_6 OUT2_9 7 7 OUT2_11 8 8 OUT2_13 9 9 OUT2_15 OUT1_1 12 12 OUT1_3 ...
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AUXOUT1 J1A J1B 1 1 AUXOUT0 IN2_0 IN2_1 2 2 IN2_2 IN2_3 3 3 IN2_4 IN2_5 4 4 IN2_6 IN2_7 5 5 IN2_8 6 6 IN2_10 IN2_9 7 7 IN2_11 IN2_12 8 8 IN2_13 IN2_14 9 9 IN2_15 10 10 ...