HS7750RKCI01H Renesas Electronics America, HS7750RKCI01H Datasheet - Page 33
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HS7750RKCI01H
Manufacturer Part Number
HS7750RKCI01H
Description
ON CHIP DEBUG EMULATOR
Manufacturer
Renesas Electronics America
Datasheets
1.HS7750RKCI01H.pdf
(264 pages)
2.HS7750RKCI01H.pdf
(38 pages)
3.HS7750RKCI01H.pdf
(9 pages)
Specifications of HS7750RKCI01H
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Table 2.10 Display Status (cont)
Item
SBTYPE (cont)
EBTYPE
STATUS
Example
B’1101
B’0000000
B’00
Description
Bit2: Read or write cycle
Bit1,0: Bus width
Displays the external bus state.
Each bit has the following meanings:
Bit5: Bus mode at DMA transfer
Displays an invalid value in the CPU access.
Bit4: CPU access or DMAC access
Bit6,3,2: One transfer unit in DMA transfer
These bits indicate memory access in the chip instead of
the bus width.
Bit1: Read or write cycle
Bit0: Bus access
If bit 0 is 0, other bits of EBTYPE and all bits of EBUS are
invalid.
Note: When bit 0 is 1 and bit 4 is 0, bits 5 and 6 become
invalid.
Displays the STATUS pin state.
0: Read cycle
1: Write cycle
Bit1=0, Bit0=0: 8-bit bus width
Bit1=0, Bit0=1: 16-bit bus width
Bit1=1, Bit0=0: 32-bit bus width
Bit1=1, Bit0=1: 64-bit bus width
0: Burst mode
1: Cycle steal mode
0: Access from CPU
1: Access from DMAC
Bit6=0, Bit3=0, Bit2=0: 64 bits
Bit6=1, Bit3=0, Bit2=0: 32 bytes
Bit6=0/1, Bit3=0, Bit2=1: 8 bits
Bit6=0/1, Bit3=1, Bit2=0: 16 bits
Bit6=0/1, Bit3=1, Bit2=1: 32 bits
0: Read cycle
1: Write cycle
0: Without bus access
1: With bus access
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