HS7750RKCI01H Renesas Electronics America, HS7750RKCI01H Datasheet - Page 29

• Manufacturer Part Number: HS7750RKCI01H
• Description: ON CHIP DEBUG EMULATOR
• Manufacturer: Renesas Electronics America

Specifications of HS7750RKCI01H

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 2.9 Performance Count Conditions
Event
Instruction cache miss
count
TLB miss count
Instruction fetch count
Instruction issue count
FPU instruction issue
count
UBC satisfaction count
Pipeline freeze due to
cache miss
Pipeline freeze cycle due
to branch instruction or
exception
Count Condition
When the TLB miss is canceled by an exception
having a higher priority than that of the TLB miss
When the instruction fetch request by the CPU is
accepted.
Counts one when two instructions are issued at the
same time.
Counts one to three when instruction fetch
exception (instruction address error, instruction
TLB miss exception, or instruction TLB protection
violation exception) occurs.
LDS Rm, FPUL, LDS.L @Rm+, FPUL, LDS Rm,
FPSCR, LDS.L @Rm+, FPSCR,
STS FPUL, Rn, STS.L FPUL, @-Rn, STS FPSCR,
Rn, STS.L FPSCR, @-Rn
Others: instructions that the instruction code is
H'Fxxx
Also counts when the emulator uses the UBC as
Break Condition 5,6.
Includes the following freeze times:
Counts only one cycle at branch instruction
execution except when the delay slot instruction is
executed with one-cycle delay. One instruction is
executed in one cycle, which is similar to the
branch count. When the instruction in the branch
destination does not exist in the instruction cache,
the delay after the second cycle is counted by the
ECF. In the PFB, all branch instructions can be
counted.
Includes instruction fetch for the cache-off area
to count the number of times the instruction has
not been fetched in one cycle.
When a cache miss occurs during an overrun
fetch generated at exception.
Counts one when two instructions are issued at
the same time.
The following shows the FPU instructions:
At internal RAM or internal I/O space access
At instruction or operand access without cache
Target Mode
EC
DT and ET
EF and EA
E
E and E2
EFP
UA and UB
PFCE and PFCD
PFB
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