M5249C3 Freescale Semiconductor, M5249C3 Datasheet - Page 58

• Manufacturer Part Number: M5249C3
• Description: KIT EVAL FOR M5249 W/ETHERNET
• Manufacturer: Freescale Semiconductor
• Series: ColdFire®r
• Type: Microprocessorr

Specifications of M5249C3

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MCF5249
• Interface Type: RS-232, Ethernet
• For Use With/related Products: MCF5249
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Hardware Description and Reconfiguration
The RESET signal is an open collector signal and so can be wire OR’ed with other reset signals from
additional peripherals.
dBUG configures the MCF5249 microprocessor internal resources during initialization. The instruction
cache is invalidated and disabled. The Vector Base Register, VBR, contains an address which initially
points to the Flash memory. The contents of the exception table are written to address $00000000 in the
SDRAM. The Software Watchdog Timer is disabled, the Bus Monitor is enabled, and the internal timers
are placed in a stop condition. The interrupt controller registers are initialised with unique interrupt
level/priority pairs. A memory map for the entire board can be seen in
3.1.3
The assertion of the HIZ signal forces all output drivers to a high-impedance state. On the M5249C3 board
the high impedance signal is pulled to +3.3V via a 4.7K pull-up resistor, ensuring that the output drivers
will not be in a high-impedance state during reset. HIZ is also available to the user on connector (J5).
3.1.4
The M5249C3 board uses a 11.2896MHz crystal (X1 on the schematics) to provide the clock to the clock
driver chip (U10). The clock driver provides a buffered clock for the MCF5249 processor (U2). In addition
to the 11.2896MHz crystal, there is also a 25MHz oscillator (U3) which feeds the Ethernet chip (U4).
3.1.5
The duration of the Watchdog is selected by the SWT[1:0] bits in the System Protection and Control
Register (SYPCR), SWT[1:0] = 11 gives a maximum timeout period of 2
monitor initialises these bits with the value 0x11, which provides the maximum time-out period, but dBUG
does NOT enable the watchdog timer via the SYPCR register SWE bit.
3.1.6
The ColdFire family of processors can receive seven levels of interrupt priorities. When the processor
receives an interrupt which has a higher priority than the current interrupt mask (in the status register), it
will perform an interrupt acknowledge cycle at the end of the current instruction cycle. This interrupt
acknowledge cycle indicates to the source of the interrupt that the request is being acknowledged and the
device should provide the proper vector number to indicate where the service routine for this interrupt level
is located. If the source of interrupt is not capable of providing a vector, its interrupt should be set up as
an autovector interrupt which directs the processor to a predefined entry in the exception table (refer to the
MCF5249 User's Manual).
The processor goes to an exception routine via the exception table. This table is stored in the Flash
EEPROM. The address of the table location is stored in the VBR. The dBUG ROM monitor writes a copy
of the exception table into the RAM starting at $00000000. To set an exception vector, the user places the
address of the exception handler in the appropriate vector in the vector table located at $00000000 and then
points the VBR to $00000000.
3-2
HIZ Signal
Clock Circuitry
Watchdog Timer
Interrupt Sources
M5249C3 User’s Manual, Rev. 1
Table
28
/System frequency. The dBUG
3-1.
Freescale Semiconductor