C8051F000DK-A Silicon Laboratories Inc, C8051F000DK-A Datasheet - Page 91
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C8051F000DK-A
Manufacturer Part Number
C8051F000DK-A
Description
DEV KIT FOR C8051F000/F001/F002
Manufacturer
Silicon Laboratories Inc
Datasheet
1.C8051F005-TB.pdf
(171 pages)
Specifications of C8051F000DK-A
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Bit7:
Bit6:
Bits5-4: UNUSED. Read = 00b, Write = don’t care.
Bits3-0: FLASCL: Flash Memory Timing Prescaler.
FOSE
R/W
Bit7
0: Flash One-shot timer disabled.
1: Flash One-shot timer enabled
0: Flash reads per one-shot timer
1: Flash always in read mode
This register specifies the prescaler value for a given system clock required to generate the
correct timing for Flash write/erase operations. If the prescaler is set to 1111b, Flash
write/erase operations are disabled.
0000: System Clock < 50kHz
0001: 50kHz System Clock < 100kHz
0010: 100kHz System Clock < 200kHz
0011: 200kHz System Clock < 400kHz
0100: 400kHz System Clock < 800kHz
0101: 800kHz System Clock < 1.6MHz
0110: 1.6MHz System Clock < 3.2MHz
0111: 3.2MHz System Clock < 6.4MHz
1000: 6.4MHz System Clock < 12.8MHz
1001: 12.8MHz System Clock < 25.6MHz
1010: 25.6MHz System Clock < 51.2MHz *
1011, 1100, 1101, 1110: Reserved Values
1111: Flash Memory Write/Erase Disabled
The prescaler value is the smallest value satisfying the following equation:
FLASCL > log
* For test purposes. The C8051F000 family is not guaranteed for operation over 25MHz.
FOSE: Flash One-Shot Timer Enable
FRAE: Flash Read Always Enable
FRAE
R/W
Bit6
Figure 11.4. FLSCL: Flash Memory Timing Prescaler
2
(System Clock / 50kHz)
R/W
Bit5
-
R/W
Bit4
-
Rev. 1.7
R/W
Bit3
R/W
Bit2
FLASCL
R/W
Bit1
R/W
Bit0
SFR Address:
Reset Value
10001111
0xB6
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