C8051F000DK-A Silicon Laboratories Inc, C8051F000DK-A Datasheet - Page 112
C8051F000DK-A
Manufacturer Part Number
C8051F000DK-A
Description
DEV KIT FOR C8051F000/F001/F002
Manufacturer
Silicon Laboratories Inc
Datasheet
1.C8051F005-TB.pdf
(171 pages)
Specifications of C8051F000DK-A
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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VDD = 2.7 to 3.6V, -40C to +85C unless otherwise specified.
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
Input Leakage Current
Capacitive Loading
Bits7-0: P3.[7:0]
Bits7-0: PRT3CF.[7:0]: Output Configuration Bits for P3.7-P3.0 (respectively)
P3.7
R/W
R/W
Bit7
Bit7
PARAMETER
(Write)
0: Logic Low Output.
1: Logic High Output (high-impedance if corresponding PRT3CF.n bit = 0)
(Read)
0: P3.n is logic low.
1: P3.n is logic high.
0: Corresponding P3.n Output mode is Open-Drain.
1: Corresponding P3.n Output mode is Push-Pull.
P3.6
R/W
R/W
Bit6
Bit6
Figure 15.14. PRT3CF: Port3 Configuration Register
Table 15.2. Port I/O DC Electrical Characteristics
P3.5
R/W
R/W
Bit5
Bit5
I
I
I
I
I
I
DGND < Port Pin < VDD, Pin Tri-state
Weak Pull-up Off
Weak Pull-up On
OH
OH
OH
OL
OL
OL
= 10uA
= 8.5mA
= 25mA
= -10uA, Port I/O push-pull
= -3mA, Port I/O push-pull
= -10mA, Port I/O push-pull
Figure 15.13. P3: Port3 Register
P3.4
R/W
R/W
Bit4
Bit4
CONDITIONS
Rev. 1.7
P3.3
R/W
R/W
Bit3
Bit3
P3.2
R/W
R/W
Bit2
Bit2
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
VDD –
VDD –
MIN
VDD
0.7 x
0.1
0.7
P3.1
R/W
R/W
Bit1
Bit1
VDD –
TYP
0.8
1.0
30
5
(bit addressable)
P3.0
R/W
R/W
Bit0
Bit0
MAX
VDD
0.3 x
0.1
0.6
1
0xB0
SFR Address:
SFR Address:
Reset Value
Reset Value
11111111
00000000
0xA7
UNITS
A
pF
V
V
V
V
112
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