Z8018100ZCO Zilog, Z8018100ZCO Datasheet - Page 43

• Manufacturer Part Number: Z8018100ZCO
• Description: Z80181 SAC APPLICATION BOARD
• Manufacturer: Zilog

Specifications of Z8018100ZCO

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: Z8018100ZC0; Z8018100ZC0

Zilog
REGISTERS FOR SYSTEM CONFIGURATION
There are four registers to determine system configuration
with the Z181. These registers are: RAM upper boundary
address register (RAMUBR, I/O address EAh), RAM lower
boundary address register (RAMLBR, I/O address EBh),
ROM address boundary register (ROMBR, I/O address
ECh) and System Configuration Register (SCR, I/O ad-
dress EDh).
ROM Address Boundary Register
(ROMBR, I/O Address ECh)
This register specifies the address range for the /ROMCS
signal. When accessed memory addresses are less than
or equal to the value programmed in this register, the
/ROMCS signal is asserted (Figure 55).
The A18 signal from the CPU is obtained before it is
multiplexed with “TOUT”. This signal can be forced to “1”
(inactive state) by setting Bit D5 of the System Configura-
tion Register, to allow the user to overlay the RAM area over
the ROM area. At power-up reset, this register contains all
1's so that /ROMCS is asserted for all addresses.
RAM Lower Boundary Address Register (RAMLBR,
Address Register (RAMUBR, I/O Address EAh)
These two registers specify the address range for the
/RAMCS signal. When accessed memory addresses are
less than or equal to the value programmed in the RAMUBR
and greater than or equal to the value programmed in the
DS971800500
I/O Address EBh) and RAM Upper Boundary
Figure 55. RAM Upper Boundary Register
EAH
7
6
5
4
3
2
1
0
A12
A13
A14
A15
A16
A17
A18
A19
PS009701-0301
RAMLBR, /RAMCS is asserted. (Figure 13) The A18 signal
from the CPU is taken before it is multiplexed with “T
In the case that these register are programmed to overlap,
/ROMCS takes priority over /RAMCS (/ROMCS is asserted
and /RAMCS is inactive).
Chip Select signals are going active for the address range:
/ROMCS: (ROMBR)
/RAMCS: (RAMUBR)
These registers are set to “FFh” at power-on Reset, and the
boundary addresses of ROM and RAM are the following:
ROM lower boundary address
(fixed) = 00000h
ROM upper boundary address
(ROMBR register) = 0FFFFFh
RAM lower boundary address
(RAMLBR register) = 0FFFFFh
RAM upper boundary address
(RAMUBR register) = 0FFFFFh
Since /ROMCS takes priority over /RAMCS, the latter will
never be asserted until the value in the ROMBR and
RAMLBR registers are re-initialized to lower values.
Figure 56. RAM Lower Boundary Register
EBH
7
6
5
4
A19-A12
A19-A12 > (RAMLBR)
3
2
1
S
MART
0
0
A
CCESS
A12
A13
A14
A15
A16
A17
A18
A19
C
ONTROLLER
Z80181
2-43
SAC
OUT
”.
™