Z8018100ZCO Zilog, Z8018100ZCO Datasheet - Page 18

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Z8018100ZCO

Manufacturer Part Number
Z8018100ZCO
Description
Z80181 SAC APPLICATION BOARD
Manufacturer
Zilog
Datasheet

Specifications of Z8018100ZCO

Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
Z8018100ZC0
Z8018100ZC0
Zilog
ASCI CHANNELS CONTROL REGISTERS
2-18
Upon RESET
Upon RESET
R/W
R/W
Bit
Bit
CNTLA1
CNTLA0
MPE
R/W
MPE
R/W
0
0
R/W
RE
R/W
0
RE
0
R/W
Figure 7. ASCI Control Register A (Ch. 0)
TE
Figure 8. ASCI Control Register A (Ch. 1)
R/W
0
TE
0
CKA1D MPBR/
/RTS0
R/W
R/W
1
1
PS009701-0301
R/W
EFR
MPBR/
R/W
EFR
x
x
MOD2 MOD1 MOD0
R/W
MOD2 MOD1 MOD0
R/W
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
0
R/W
R/W
0
0
1
1
0
0
1
1
0
0
0
1
1
0
0
1
1
0
Addr 01h
Addr 00h
R/W
R/W
0 Start + 7-Bit Data + 1 Stop
1 Start + 7-Bit Data + 2 Stop
0 Start + 7-Bit Data + Parity + 1 Stop
1 Start + 7-Bit Data + Parity + 2 Stop
0 Start + 8-Bit Data + 1 Stop
1 Start + 8-Bit Data + 2 Stop
0 Start + 8-Bit Data + Parity + 1 Stop
1 Start + 8-Bit Data + Parity + 2 Stop
0
0 Start + 7-Bit Data + 1 Stop
1 Start + 7-Bit Data + 2 Stop
0 Start + 7-Bit Data + Parity + 1 Stop
1 Start + 7-Bit Data + Parity + 2 Stop
0 Start + 8-Bit Data + 1 Stop
1 Start + 8-Bit Data + 2 Stop
0 Start + 8-Bit Data + Parity + 1 Stop
1 Start + 8-Bit Data + Parity + 2 Stop
0
MODE Selection
MODE Selection
Read - Multiprocessor Bit Receive
Write - Error Flag Reset
CKA1 Disable
Transmit Enable
Receive Enable
Multiprocessor Enable
Read - Multiprocessor Bit Receive
Write - Error Flag Reset
Request To Send
Transmit Enable
Receive Enable
Multiprocessor Enable
S
MART
A
CCESS
C
DS971800500
ONTROLLER
Z80181
SAC

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