Z86E4000ZDV Zilog, Z86E4000ZDV Datasheet - Page 40

• Manufacturer Part Number: Z86E4000ZDV
• Description: 44 PIN PLCC ADAPTER
• Manufacturer: Zilog

Specifications of Z86E4000ZDV

• Convert From (adapter End): 40-Pin DIP ZIF Socket
• Convert To (adapter End): 44-PLCC Plug
• For Use With/related Products: Zilog Emulators/Programmers
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-2015

FUNCTIONAL DESCRIPTION (Continued)
Z86E30/E31/E40
Z8 4K OTP Microcontroller
Power-On Reset (POR). A timer circuit clocked by a ded-
icated on-board RC oscillator is used for the Power-On Re-
set (POR) timer function. The POR timer allows V
the oscillator circuit to stabilize before instruction execu-
tion begins.
The POR timer circuit is a one-shot timer triggered by one
of three conditions:
1. Power fail to Power OK status
2. Stop-Mode Recovery (if D5 of SMR=0)
3. WDT time-out
The POR time is a nominal 5 ms. Bit 5 of the STOP mode
Register (SMR) determines whether the POR timer is by-
passed after STOP-Mode Recovery (typical for an external
clock and RC/LC oscillators with fast start up times).
HALT. Turns off the internal CPU clock, but not the XTAL
oscillation. The counter/timers and external interrupt IRQ0,
IRQ1, and IRQ2 remain active. The device is recovered by
interrupts, either externally or internally generated. An in-
terrupt request must be executed (enabled) to exit HALT
Mode. After the interrupt service routine, the program con-
tinues from the instruction after the HALT.
40
PCON (FH) 00H
D7 D6 D5 D4 D3 D2 D1 D0
* Default Setting After Reset
Figure 30. Port Configuration Register (PCON)
P R E L I M I N A R Y
CC
(Write Only)
and
In order to enter STOP or HALT Mode, it is necessary to
first flush the instruction pipeline to avoid suspending exe-
cution in mid-instruction. To do this, the user must execute
a NOP (Opcode=FFH) immediately before the appropriate
sleep instruction, that is:
STOP. This instruction turns off the internal clock and ex-
ternal crystal oscillation and reduces the standby current
to 10 microamperes or less. STOP Mode is terminated by
one of the following resets: either by WDT time-out, POR,
a Stop-Mode Recovery Source, which is defined by the
SMR register or external reset. This causes the processor
to restart the application program at address 000CH.
Port Configuration Register (PCON). The PCON regis-
ter configures the ports individually; comparator output on
Port 3, open-drain on Port 0 and Port 1, low EMI on Ports
0, 1, 2 and 3, and low EMI oscillator. The PCON register is
located in the expanded register file at Bank F, location 00
(Figure 30).
0 Port 1 Open Drain
1 Port 1 Push-pull Active*
Comparator Output Port 3
0 P34, P37 Standard Output*
1 P34, P37 Comparator Output
0 Port 0 Low EMI
1 Port 0 Standard*
0 Port 1 Low EMI
1 Port 1 Standard*
0 Port 2 Low EMI
1 Port 2 Standard*
0 Port 3 Low EMI
1 Port 3 Standard*
0 Port 0 Open Drain
1 Port 0 Push-pull Active*
Low EMI Oscillator
0 Low EMI
1 Standard*
FF
6F
FF
7F
STOP
HALT
NOP
NOP
or
; clear the pipeline
; enter STOP Mode
; clear the pipeline
; enter HALT Mode
DS97Z8X0502
Zilog