EVAL-AD7716EBZ Analog Devices Inc, EVAL-AD7716EBZ Datasheet - Page 4

• Manufacturer Part Number: EVAL-AD7716EBZ
• Description: BOARD EVAL FOR AD7716
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD7716EBZ

• Number Of Adc's: *
• Number Of Bits: *
• Sampling Rate (per Second): *
• Data Interface: *
• Inputs Per Adc: *
• Input Range: *
• Power (typ) @ Conditions: *
• Voltage Supply Source: *
• Operating Temperature: *
• Utilized Ic / Part: AD7716
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Parameter
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
NOTES
1
2
3
4
5
6
7
AD7716
MASTER MODE TIMING CHARACTERISTICS
f
back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish
time of the part and as such is independent of external bus loading capacitances.
CLKIN
r
f
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Sample tested at +25 C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
See Figures 1 and 3.
CLKIN duty cycle range is 40% to 60%.
The AD7716 is production tested with f
Specified using 10% and 90% points on waveform of interest.
t
t
CLKIN
5
5
16
17
6
7
is measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
= 8 MHz; Input Levels: Logic 0 = 0 V, Logic 1 = DV
3, 4
CASCOUT (O)
CASCIN (I)
SDATA (O)
Limit at T
(B Version)
400
8
40
40
1/f
1/f
1/2f
50
40
50
1/f
40
1/f
45
1/2f
1/2f
1/2f
50
20
1/2f
2/f
DRDY (O)
SCLK (O)
CLKIN (I)
RFS (O)
CLKIN
CLKIN
CLKIN
CLKIN
CLKIN
CLKIN
CLKIN
CLKIN
CLKIN
CLKIN
+ 30
+ 50
+ 10
+ 50
+ 60
MIN
, T
CLKIN
MAX
t
t
7
10
t
8
at 8 MHz in the slave mode. It is guaranteed by characterization to operate at 400 kHz and 8 MHz in master mode.
t
9
t
16
Units
kHz min
MHz max
ns max
ns max
ns min
ns min
ns max
ns max
ns max
ns min
ns
ns max
ns
ns max
ns max
ns min
ns max
ns max
ns min
ns max
ns
Figure 3. Master Mode Timing Diagram
DB31
CH1
DD
; unless otherwise noted)
t
11
DB30
CH1
t
12
t
1, 2
12
–4–
DB29
CH1
Conditions/Comments
CLKIN Frequency
Digital Output Rise Time. Typically 20 ns
Digital Output Fall Time. Typically 20 ns
CASCIN Pulse Width
CASCIN to DRDY Setup Time
DRDY Low to SCLK Low Delay
CLKIN High to DRDY Low, SCLK Active, RFS Active
CLKIN High to SCLK High Delay
SCLK Width
SCLK Period
SCLK High to RFS High Delay
RFS Pulse Width
SCLK High to SDATA Valid Delay
SCLK Low to SDATA High Impedance Delay
CLKIN High to DRDY High Delay
CLKIN High to RFS High Impedance, SCLK High Impedance
SCLK Low to CASCOUT High Delay
CASCOUT Pulse Width
(AV
DD
DB25
t
CH1
14
= DV
t
13
DD
DB24
CH1
t
= +5 V
15
DB23
CH1
5%; AV
DB2
CH4
SS
= –5 V
DB1
CH4
DB0
CH4
5%; AGND = DGND = 0 V;
t
t
17
20
t
18
t
t
t
19
19
21
REV. A