AD9514/PCB Analog Devices Inc, AD9514/PCB Datasheet
AD9514/PCB
Specifications of AD9514/PCB
Related parts for AD9514/PCB
AD9514/PCB Summary of contents
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FEATURES 1.6 GHz differential clock input 3 programmable dividers Divide-by in range from1 to 32 Phase select for coarse delay adjust 2 independent 1.6 GHz LVPECL clock outputs Additive broadband output jitter 225 fs rms 1 independent 800 MHz/250 MHz ...
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AD9514 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Clock Input.................................................................................... 3 Clock Outputs ............................................................................... 3 Timing Characteristics ................................................................ 4 Clock Output Phase Noise .......................................................... ...
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SPECIFICATIONS Typical (typ) is given for V = 3.3 V ± 5 and maximum (max) values are given over full V CLOCK INPUT Table 1. Parameter CLOCK INPUT (CLK) Input Frequency 1 1 Input Sensitivity Input Common-Mode Voltage, ...
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AD9514 TIMING CHARACTERISTICS CLK input slew rate = 1 V/ns or greater. Table 3. Parameter LVPECL Output Rise Time Output Fall Time PROPAGATION DELAY CLK-TO-LVPECL OUT PECL Divide = 1 Divide = 2 − ...
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Parameter Zero Scale Delay Time Zero Scale Variation with Temperature 3 Full Scale Time Delay Full Scale Variation with Temperature Linearity, DNL Linearity, INL 1 This is the difference between any two similar delay paths within ...
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AD9514 Parameter CLK = 491.52 MHz, OUT = 245.76 MHz Divide = Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset >1 MHz Offset CLK = 245.76 MHz, ...
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Parameter CLK = 491.52 MHz, OUT = 122.88 MHz Divide = Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLK ...
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AD9514 Parameter CLK = 78.6432 MHz, OUT = 78.6432 MHz Divide = Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset ...
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Parameter CLK = 400 MHz LVDS (OUT2) = 100 MHz Divide = 4 Both LVPECL = 50 MHz CMOS OUTPUT ADDITIVE TIME JITTER CLK = 400 MHz CMOS (OUT2) = 100 MHz Divide = 4 CLK = 400 MHz CMOS ...
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AD9514 SYNCB, VREF, AND SETUP PINS Table 6. Parameter Min SYNCB Logic High 2.7 Logic Low Capacitance VREF Output Voltage 0. S10 Levels 0 1/3 0 2 ...
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TIMING DIAGRAMS t CLK CLK t PECL t LVDS t CMOS Figure 2. CLK/CLKB to Clock Output Timing, Divide = 1 Mode DIFFERENTIAL 80% LVPECL 20 Figure 3. LVPECL Timing, Differential DIFFERENTIAL 20% SINGLE-ENDED 20 Rev. ...
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AD9514 ABSOLUTE MAXIMUM RATINGS Table 8. With Respect to Parameter or Pin VS GND RSET GND CLK GND CLK CLKB OUT0, OUT1, OUT2 GND FUNCTION GND STATUS GND 1 Junction Temperature Storage Temperature Lead Temperature (10 sec) ESD CAUTION ESD ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VS 1 CLK 2 CLKB 3 AD9514 VS 4 TOP VIEW (Not to Scale) SYNCB 5 VREF 6 S10 Figure 6. 32-Lead LFCSP Pin Configuration Note that the exposed paddle on this ...
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AD9514 TERMINOLOGY Phase Jitter and Phase Noise An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0 to 360 degrees for each cycle. Actual signals, however, display a certain ...
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TYPICAL PERFORMANCE CHARACTERISTICS 0.4 2 LVPECL (DIV ON) 0.3 2 LVPECL (DIV = 1) 0.2 1 LVDS (DIV ON) 0.1 400 800 OUTPUT FREQUENCY (MHz) Figure 8. Power vs. Frequency—LVPECL, LVDS START 300kHz STOP 5GHz Figure 9. CLK Smith Chart ...
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AD9514 VERT 500mV/DIV Figure 11. LVPECL Differential Output @ 1600 MHz VERT 100mV/DIV Figure 12. LVDS Differential Output @ 800 MHz VERT 500mV/DIV Figure 13. CMOS Single-Ended Output @ 250 MHz with 10 pF Load 1.8 1.7 1.6 1.5 1.4 ...
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OFFSET (Hz) Figure 17. Additive Phase Noise—LVPECL Divide = 1, 245.76 MHz –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 10 100 1k 10k 100k OFFSET ...
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AD9514 FUNCTIONAL DESCRIPTION OVERALL The AD9514 provides for the distribution of its input clock three outputs simultaneously. OUT0 and OUT1 are LVPECL levels. OUT2 can be set to either LVDS or CMOS levels. Each output has its ...
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Synchronization is initiated by pulling the SYNCB pin low for a minimum of 5 ns. The input clock does not have to be present at the time the command is issued. The synchronization occurs after four input clock cycles. The ...
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AD9514 Table 10. S0—OUT2 Delay S0 Delay Full Scale 0 Off (Bypassed) 1/3 1 Table 11. S1, S2—Output Select OUT0 OUT1 S1 S2 LVPECL LVPECL 0 0 OFF 410 mV 1/3 0 790 ...
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Table 13. S5, S6—OUT2 Divide or OUT1 Phase S2 ≠ 0 OUT2 Divide (Duty Cycle ) 1 (50%) 2 (33 (50%) 0 1/3 5 (40%) 1/3 1/3 ...
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AD9514 DIVIDER PHASE OFFSET The phase of OUT1 or OUT2 can be selected, depending on the divide ratio and output configuration chosen. This allows, for example, the relative phase of OUT0 and OUT1 to be set. After a SYNC operation ...
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... PCB. The power supply should be bypassed on the PCB with adequate capacitance (>10 μF). The AD9514 should be bypassed with adequate capacitors (0.1 μF) at all power pins as close as possible to the part. The layout of the AD9514 evaluation board (AD9514/PCB good example. OUT OUTB OUT OUTB Rev ...
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... PCB. This requires a grid of vias from the top layer down to the ground plane (see Figure 34). The AD9514 evaluation board (AD9514/PCB) provides a good example of how the part should be attached to the PCB. VIAS TO GND PLANE Figure 34. PCB Land for Attaching Exposed Paddle ...
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APPLICATIONS USING THE AD9514 OUTPUTS FOR ADC CLOCK APPLICATIONS Any high speed, analog-to-digital converter (ADC) is extremely sensitive to the quality of the sampling clock provided by the user. An ADC can be thought sampling mixer, and ...
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AD9514 LVDS CLOCK DISTRIBUTION The AD9514 provides one clock output (OUT2) that is selectable as either CMOS or LVDS levels. Low voltage differential signaling ( LVDS differential output option for OUT2. LVDS uses a current mode output stage. ...
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PHASE NOISE AND JITTER MEASUREMENT SETUPS WENZEL EVALUATION BOARD OSCILLATOR SPLITTER 0° ZESC-2-11 EVALUATION BOARD WENZEL OSCILLATOR ⎡ V ⎢ A_RMS ⎢ ⎣ J_RMS where the rms time jitter. j_RMS SNR is the signal-to-noise ratio. ...
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... ORDERING GUIDE Model Temperature Range 1 AD9514BCPZ −40°C to +85°C 1 AD9514BCPZ-REEL7 −40°C to +85°C AD9514/PCB Pb-free part. © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 5.00 0.60 MAX 0.50 BSC TOP 4 ...