AD9514/PCB Analog Devices Inc, AD9514/PCB Datasheet - Page 13

• Manufacturer Part Number: AD9514/PCB
• Description: BOARD EVAL CLOCK 3CHAN 32LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9514/PCB

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Note that the exposed paddle on this package is an electrical connection as well as a thermal enhancement. For the device to
function properly, the paddle must be soldered to a PCB land that functions as both a heat dissipation path as well as an electrical
ground (analog).
Table 9. Pin Function Descriptions
Pin No.
1, 4 ,17, 20, 21,
24, 26, 29, 30
2
3
5
6
7 to 16, 25
18
19
22
23
27
28
31, Exposed Paddle
32
SYNCB
CLKB
VREF
CLK
S10
VS
VS
S9
1
2
4
5
6
7
8
3
Figure 6. 32-Lead LFCSP Pin Configuration
Mnemonic
VS
CLK
CLKB
SYNCB
VREF
S10 to S0
OUT2B
OUT2
OUT1B
OUT1
OUT0B
OUT0
GND
RSET
(Not to Scale)
AD9514
TOP VIEW
Description
Power Supply (3.3 V).
Clock Input.
Complementary Clock Input.
Used to Synchronize Outputs; Do Not Let Float.
Provides 2/3 V
Setup Select Pins. These are 4-state logic. The logic levels are V
The VREF pin provides 2/3 V
that logic level should be left no connection (NC).
Complementary LVDS/Inverted CMOS Output.
LVDS/CMOS Output.
Complementary LVPECL Output.
LVPECL Output.
Complementary LVPECL Output.
LVPECL Output.
Ground. The exposed paddle on the back of the chip is also GND.
Current Sets Resistor to Ground. Nominal value = 4.12 kΩ.
24 VS
23 OUT1
22 OUT1B
21 VS
20 VS
19 OUT2
18 OUT2B
17 VS
S
for Use as One of the Four Logic Levels on S0 to S10.
Rev. 0 | Page 13 of 28
S
. Each pin is internally biased to 1/3 V
24
17
16
THERMAL CONNECTION
IS AN ELECTRICAL AND
25
THE EXPOSED PADDLE
Figure 7. Exposed Paddle
(BOTTOM VIEW)
EXPOSED PAD
S
, GND, 1/3 V
GND
S
so that a pin requiring
S
32
, and 2/3 V
9
1
8
S
.
AD9514