EVAL-AD73360LEB Analog Devices Inc, EVAL-AD73360LEB Datasheet - Page 3

• Manufacturer Part Number: EVAL-AD73360LEB
• Description: BOARD EVAL FOR AD73360L
• Manufacturer: Analog Devices Inc
• Type: ADC + DAC, Codec, Front Endr

Specifications of EVAL-AD73360LEB

• Rohs Status: RoHS non-compliant
• Contents: Evaluation Board
• For Use With/related Products: AD73360L
• Lead Free Status / RoHS Status: Not Compliant

Parameter
LOGIC OUTPUT
POWER SUPPLIES
NOTES
1
2
3
4
5
6
7
8
Specifications subject to change without notice.
TIMING CHARACTERISTICS
Parameter
Clock Signals
Serial Port
Operating temperature range is as follows: –40°C to +85°C. Therefore, T
Test conditions: Input PGA set for 0 dB gain (unless otherwise noted).
At input to sigma-delta modulator of ADC.
Guaranteed by design.
Overall group delay will be affected by the sample rate and the external digital filtering.
The ADC’s input impedance is inversely proportional to DMCLK and is approximated by: (4 × 10
Frequency response of ADC measured with input at audio reference level (the input level that produces an output level of –10 dBm0), with 38 dB preamplifier
Test Conditions: no load on digital inputs, analog inputs ac-coupled to ground.
bypassed and input gain of 0 dB.
V
V
Three-State Leakage Current
AVDD1, AVDD2
DVDD
I
t
t
t
t
t
t
t
t
t
t
t
t
t
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
OH
OL
8
, Output Low Voltage
, Output High Voltage
Conditions
ADCs Only On
REFCAP Only On
REFCAP and REFOUT Only On
All Sections On
All Sections Off
All Sections Off
The above values are in mA and are typical values unless otherwise noted. MCLK = 16.384 MHz; SCLK = 16.384 MHz.
Limit at
T
61
24.4
24.4
t
0.4 × t
0.4 × t
20
0
10
10
10
10
30
1
A
= –40 C to +85 C
1
1
Table I. Current Summary (AVDD = DVDD = 3.3 V)
(AVDD = 2.7 V to 3.6 V; DVDD = 2.7 V to 3.6 V; AGND = DGND = 0 V; T
wise noted.)
Total
Current
(Max)
25
1.0
3.5
26.5
1.0
0.05
Min
V
0
–10
2.7
2.7
DD
– 0.4
AD73360LA
1
0
0
Typ
SE
0
0
1
MIN
= –40°C and T
MCLK
ON
Yes
No
No
Yes
Yes
No
Max
V
0.4
+10
3.6
3.6
DD
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns max
ns max
ns max
MAX
Comments
REFOUT Disabled
REFOUT Disabled
REFOUT Enabled
MCLK Active Levels Equal to 0 V and DVDD
Digital Inputs Static and Equal to 0 V or DVDD
Unit
V
V
µA
V
V
= +85°C.
11
)/DMCLK.
Test Conditions/Comments
|IOUT| ≤ 100 µA
|IOUT| ≤ 100 µA
See Table I
Description
See Figure 1.
MCLK Period
MCLK Width High
MCLK Width Low
See Figures 3 and 4.
SCLK Period
SCLK Width High
SCLK Width Low
SDI/SDIFS Setup before SCLK Low
SDI/SDIFS Hold after SCLK Low
SDOFS Delay from SCLK High
SDOFS Hold after SCLK High
SDO Hold after SCLK High
SDO Delay from SCLK High
SCLK Delay from MCLK
A
= T
MlN
to T
MAX
AD73360L
, unless other-