AD9858/FDPCB Analog Devices Inc, AD9858/FDPCB Datasheet - Page 7

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AD9858/FDPCB

Manufacturer Part Number
AD9858/FDPCB
Description
BOARD EVAL FOR AD9858/FD
Manufacturer
Analog Devices Inc
Datasheets

Specifications of AD9858/FDPCB

Rohs Status
RoHS non-compliant
Design Resources
Low Jitter Sampling Clock Generator for High Performance ADCs Using AD9958/9858 and AD9515 (CN0109)
Lead Free Status / Rohs Status
Not Compliant
AD9858FDPCB
PLL FAST LOCK
This window is accessible from the Control window or from the View menu. The PLL Fast Lock window allows the user to enable and
disable the PLL Fast Lock algorithm. When engaged, the charge pump operates in three modes: a frequency detect mode, a wide closed-
loop mode, and a final closed-loop mode. The user programs the charge pump reference current with an external resistor from CP_Iset to
ground. Here, the user tells the program what value is used (2400 Ω is the default value on the evaluation board) and then programs the
scaling factors the device should use for the different modes. The user can also set the Phase Detector Divider Ratio. This divisor scales
the divider input in time.
Figure 10. PLL Fast Lock Window
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