AD9748ACP-PCB Analog Devices Inc, AD9748ACP-PCB Datasheet - Page 8

• Manufacturer Part Number: AD9748ACP-PCB
• Description: BOARD EVAL FOR AD9748ACP
• Manufacturer: Analog Devices Inc
• Series: TxDAC®r

Specifications of AD9748ACP-PCB

• Rohs Status: RoHS non-compliant
• Number Of Dac's: 1
• Number Of Bits: 8
• Outputs And Type: 1, Differential
• Sampling Rate (per Second): 210M
• Data Interface: Parallel
• Settling Time: 11ns
• Dac Type: Current
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9748

AD9748
TERMINOLOGY
Linearity Error (Also Called Integral Nonlinearity or INL)
Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero to full scale.
Differential Nonlinearity (or DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
Monotonicity
A DAC is monotonic if the output increases or remains constant
as the digital input increases.
Offset Error
The deviation of the output current from the ideal of zero is
called the offset error. For IOUTA, 0 mA output is expected
when the inputs are all 0s. For IOUTB, 0 mA output is expected
when all inputs are set to 1s.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s.
Output Compliance Range
The range of allowable voltage at the output of a current output
DAC. Operation beyond the maximum compliance limits can
cause either output stage saturation or breakdown, resulting in
nonlinear performance.
Temperature Drift
Temperature drift is specified as the maximum change from the
ambient (25°C) value to the value at either T
and gain drift, the drift is reported in ppm of full-scale range (FSR)
per °C. For reference drift, the drift is reported in ppm per °C.
DCOM
DVDD
*AWG2021 CLOCK
RETIMED SO THAT
THE DIGITAL DATA
TRANSITIONS ON
FALLING EDGE OF
50% DUTY CYCLE
CLOCK.
RETIMED
OUTPUT*
CLOCK
PULSE GENERATOR
LECROY 9210
50Ω
R
SET
0.1μF
3.3V
3.3V
CLK+
CLK–
OUTPUT
CLOCK
REFIO
FS ADJ
DVDD
DCOM
CLKVDD
CLKCOM
SLEEP
1.2V REF
Figure 4. Basic AC Characterization Test Setup (SOIC/TSSOP Packages)
MIN
DIGITAL DATA INPUTS (DB7–DB0)
SEGMENTED
or T
SWITCHES
TEKTRONIX AWG-2021
MAX
WITH OPTION 4
150pF
. For offset
LATCHES
DIGITAL
DATA
CURRENT
SOURCE
SWITCHES
ARRAY
Rev. A | Page 8 of 24
LSB
3.3V
AVDD
AD9748
ACOM
IOUTA
IOUTB
Power Supply Rejection
The maximum change in the full-scale output as the supplies
are varied from nominal to minimum and maximum specified
voltages.
Settling Time
The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.
Spurious-Free Dynamic Range
The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified
bandwidth.
T
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured input signal. It is
expressed as a percentage or in decibels (dB).
Multitone Power Ratio
The spurious-free dynamic range containing multiple carrier
tones of equal amplitude. It is measured as the difference
between the rms amplitude of a carrier tone to the peak
spurious signal in the region of a removed tone.
o tal Harmonic Distortion (THD)
T
MODE
CMODE
50Ω
20pF
50Ω
20pF
100Ω
MINI-CIRCUITS
T1-1T
ROHDE & SCHWARZ
FSEA30
SPECTRUM
ANALYZER