AD8327-EVAL Analog Devices Inc, AD8327-EVAL Datasheet - Page 8

• Manufacturer Part Number: AD8327-EVAL
• Description: BOARD EVAL FOR AD8327
• Manufacturer: Analog Devices Inc
• Type: Video Processorr

Specifications of AD8327-EVAL

• Rohs Status: RoHS non-compliant
• Contents: Evaluation Board
• For Use With/related Products: AD8327
• Lead Free Status / RoHS Status: Not Compliant

AD8327
APPLICATIONS
General Application
The AD8327 is primarily intended for use as the upstream power
amplifier (PA), also known as a line driver, in DOCSIS (Data
Over Cable Service Interface Specification) certified cable
modems and CATV set-top boxes. The upstream signal is either
a QPSK or QAM signal generated by a DSP, a dedicated QPSK/
QAM modulator, or a DAC.
In all cases the signal must be low-pass filtered before being
applied to the PA in order to filter out-of-band noise and higher
order harmonics from the amplified signal. Due to the varying
distances between the cable modem and the headend, the
upstream PA must be capable of varying the output power by
applying gain or attenuation. The varying output power of the
AD8327 ensures that the signal from the cable modem will have
the proper level once it arrives at the headend. The upstream
signal path commonly includes a diplexer and cable splitters.
The AD8327 has been designed to overcome losses associated
with these passive components in the upstream cable path.
Circuit Description
The AD8327 is composed of three analog functions in the power-
up or forward mode. The input amplifier (preamp) can be used
single-ended or differentially. If the input is used in the differen-
tial configuration, it is imperative that the input signals be 180
degrees out of phase and of equal amplitude. The preamp stage
drives a DAC, which provides the AD8327’s attenuation (eight
bits or 48.16 dB). The signals in the preamp and DAC gain
blocks are differential to improve the PSRR and linearity.
A differential current is fed from the DAC into the output stage,
Decimal Code
0
1
2
4
8
16
32
64
128
Bit 7
0
0
0
0
0
0
0
0
1
Bit 6
0
0
0
0
0
0
0
1
0
Bit 5
0
0
0
0
0
0
1
0
0
Table I. Gain States
Bit 4
0
0
0
0
0
1
0
0
0
which amplifies these currents to the appropriate levels necessary to
drive a 75 Ω load. The output stage maintains 75 Ω output
impedance, eliminating the need for external matching resistors.
SPI Programming and Gain Adjustment
The AD8327 is controlled through a serial peripheral interface
(SPI) of three digital data lines: CLK, DATEN, and SDATA.
Changing the gain requires eight bits of data to be streamed into
the SDATA port. The sequence of loading the SDATA register
begins on the falling edge of the DATEN pin, which activates
the CLK line. With the CLK line activated, data on the SDATA
line is clocked into the serial shift register, Most Significant Bit
(MSB) first, on the rising edge of the CLK pulses. The 8-bit
data word is latched into the attenuator core on the rising edge
of the DATEN line. This provides control over the changes in
the output signal level. The serial interface timing for the AD8327
is shown in Figures 2 and 3. The programmable gain range of
the AD8327 is –18.16 dB to +30 dB with steps of 6.02 dB per
major carry. This provides a total gain range of 48.16 dB.
The AD8327 was characterized with a TOKO transformer
(TOKO#617DB-A0070) on the input, and the stated gain
values account for the losses due to the transformer. Table I
shows the possible gain states.
Input Bias, Impedance, and Termination
The V
the input signal should be ac-coupled using 0.1 µF capacitors as
seen in the typical application circuit (see Figure 4). The differ-
ential input impedance of the AD8327 is approximately 1.6 kΩ,
while the single-ended input impedance is 800 Ω.
Bit 3
0
0
0
0
1
0
0
0
0
IN+
and V
Bit 2
0
0
0
1
0
0
0
0
0
IN–
inputs have a dc bias level of V
Bit 1
0
0
1
0
0
0
0
0
0
Bit 0
0
1
0
0
0
0
0
0
0
Gain
–18.16
–12.14
–6.12
–0.10
5.92
11.94
17.96
23.98
30
CC
/2, therefore