AD8327-EVAL Analog Devices Inc, AD8327-EVAL Datasheet - Page 10

• Manufacturer Part Number: AD8327-EVAL
• Description: BOARD EVAL FOR AD8327
• Manufacturer: Analog Devices Inc
• Type: Video Processorr

Specifications of AD8327-EVAL

• Rohs Status: RoHS non-compliant
• Contents: Evaluation Board
• For Use With/related Products: AD8327
• Lead Free Status / RoHS Status: Not Compliant

Power Supply
The 5 V supply should be delivered to each of the V
low impedance power bus to ensure that each pin is at the same
potential. The power bus should be decoupled to ground using
a 10 µF tantalum capacitor located close to the AD8327ARU.
In addition to the 10 µF capacitor, each V
individually decoupled to ground with 0.1 µF ceramic chip capaci-
tors located close to the pins. The bypass pin, labeled BYP (Pin 14),
should also be decoupled with a 0.1 µF capacitor. The PCB
should have a low impedance ground plane covering all unused
portions of the board, except in areas of the board where input
and output traces are in close proximity to the AD8327. All
AD8327 ground pins must be connected to the ground plane to
ensure proper grounding of all internal nodes.
CXR Pin
The AD8327 features internal circuitry that controls burst
transients. This feature uses a 100 pF capacitor connected to
Pin 7 of the AD8327, to slow down the turn-on transient and
minimize between-burst transients.
Signal Integrity Layout Considerations
Careful attention to printed circuit board layout details will
prevent problems due to board parasitics. Proper RF design
techniques are mandatory. The differential input and output
traces should be kept as short as possible. It is also critical that
all differential signal paths be symmetrical in length and width.
In addition, the input and output traces should be kept far apart,
to minimize coupling (crosstalk) through the board. Following
these guidelines will optimize the overall performance of the
AD8327 in all applications.
Initial Power-Up
When the supply voltage is first applied to the AD8327, the gain
of the amplifier is initially set to gain code 0. As power is first
applied to the amplifier, the TXEN pin should be held low
(Logic 0) to prevent forward signal transmission. After power
has been applied to the amplifier, the gain can be set to the
desired level by following the procedure provided in the SPI
Programming and Gain Adjustment section. The TXEN pin
can then be brought from Logic 0 to Logic 1, enabling forward
signal transmission at the desired gain level.
AD8327
ZIN ( )
50
75
100
150
ZIN ( )
50
75
Table II. Common Input Terminations
Single-Ended Input Termination
Differential Input Termination
R11
Open
Open
Open
Open
R11 ( )
25.5
39.2
R12
Open
Open
Open
Open
R12 ( )
53.6
82.5
CC
pin should be
CC
pins via a
R13 ( )
52.1
78.7
107
165
R13
Open
Open
Asynchronous Power-Down
The asynchronous TXEN pin is used to place the AD8327 into
between-burst mode, while maintaining a differential output
impedance of 75 Ω. Applying Logic 0 to the TXEN pin activates
the on-chip reverse amplifier, providing an 86% reduction in
consumed power. For 5 V operation, the supply current is typically
reduced from 105 mA to 15 mA. In this mode of operation,
between-burst noise is minimized and the amplifier can no longer
transmit in the upstream direction. In addition to the TXEN
pin, the AD8327 also incorporates an asynchronous SLEEP pin,
which may be used to further reduce the supply current to
approximately 5 mA. Applying Logic 0 to the SLEEP pin places
the amplifier into SLEEP mode. Transitioning into or out of
SLEEP mode may result in a transient voltage at the output of
the amplifier.
Distortion, Adjacent Channel Power, and DOCSIS
In order to deliver the DOCSIS required +58 dBmV of QPSK
signal and +55 dBmV of 16 QAM signal, the PA is required to
deliver up to +60 dBmV and +57 dBmV respectively. This level is
required to compensate for losses associated with the diplex filter
or other passive components that may be included in the upstream
path of cable modems or set-top boxes. It should be noted that
the AD8327 was characterized with the TOKO 617DB-A0070
transformer on the input to generate a differential input signal.
TPC 7 and TPC 10 show the AD8327 second and third order
harmonic distortion performance versus fundamental frequency
for various output power levels. These figures are useful for
determining the in-band harmonic levels from 5 MHz to 65 MHz.
Harmonics higher in frequency (above 42 MHz for DOCSIS
and above 65 MHz for EuroDOCSIS) will be sharply attenuated
by the low-pass filter function of the diplexer.
Another measure of signal integrity is adjacent channel power,
commonly referred to as ACP. DOCSIS section 4.2.10.1.1 states,
“Spurious emissions from a transmitted carrier may occur in an
adjacent channel that could be occupied by a carrier of the same or
different symbol rates.” TPC 13 shows the measured ACP for a
+57 dBmV 16 QAM signal taken at the output of the AD8327
evaluation board, through a 75 Ω to 50 Ω matching pad (5.7 dB of
loss). The transmit channel width and adjacent channel width in
TPC 13 correspond to symbol rates of 160 K
the ACP results for the AD8327 driving a 16 QAM, +57 dBmV
signal for all conditions in DOCSIS Table 4-7 “Adjacent Channel
Spurious Emissions.”
TRANSMIT
SYMBOL
RATE
160 K
320 K
640 K
1280 K
2560 K
SYM/SEC
SYM/SEC
SYM/SEC
SYM/SEC
SYM/SEC
160 K
Table III. Adjacent Channel Power
(dBc)
–62
–62
–63
–64
–66
ACP
SYM/SEC
320 K
–63
–63
–62
–63
–63
ADJACENT CHANNEL SYMBOL RATE
(dBc)
ACP
SYM/SEC
640 K
(dBc)
–65
–64
–63
–63
–63
ACP
SYM/SEC
SYM/S
1280 K
(dBc)
–66
–66
–65
–63
–62
ACP
SYM/SEC
. Table III shows
2560 K
–66
–66
–66
–64
–63
(dBc)
ACP
SYM/SEC