AD8323-EVAL Analog Devices Inc, AD8323-EVAL Datasheet - Page 7

• Manufacturer Part Number: AD8323-EVAL
• Description: BOARD EVAL FOR AD8323
• Manufacturer: Analog Devices Inc
• Type: Video Processorr

Specifications of AD8323-EVAL

• Rohs Status: RoHS non-compliant
• Contents: Evaluation Board
• For Use With/related Products: AD8322

APPLICATIONS
General Application
The AD8323 is primarily intended for use as the upstream
power amplifier (PA) in DOCSIS (Data Over Cable Service
Interface Specifications) certified cable modems and CATV set-
top boxes. Upstream data is modulated in QPSK or QAM for-
mat, and done with DSP or a dedicated QPSK/QAM modulator.
The amplifier receives its input signal from the QPSK/QAM
modulator or from a DAC. In either case the signal must be
low-pass filtered before being applied to the amplifier. Because
the distance from the cable modem to the central office will vary
with each subscriber, the AD8323 must be capable of varying its
output power by applying gain or attenuation to ensure that all
signals arriving at the central office are of the same amplitude.
The upstream signal path contains components such as a trans-
former and diplexer that will result in some amount of power loss.
Therefore, the amplifier must be capable of providing enough
power into a 75 Ω load to overcome these losses without sacri-
ficing the integrity of the output signal.
Operational Description
The AD8323 is composed of four analog functions in the
power-up or forward mode. The input amplifier (preamp) can
be used single-ended or differentially. If the input is used in
the differential configuration, it is imperative that the input
signals are 180 degrees out of phase and of equal amplitudes.
This will ensure the proper gain accuracy and harmonic
performance. The preamp stage drives a vernier stage that
provides the fine tune gain adjustment. The 0.7526 dB step
resolution is implemented in this stage and provides a total of
approximately 5.25 dB of attenuation. After the vernier stage,
a DAC provides the bulk of the AD8323’s attenuation (8 bits
or 48 dB). The signals in the preamp and vernier gain blocks
are differential to improve the PSRR and linearity. A differen-
tial current is fed from the DAC into the output stage, which
amplifies these currents to the appropriate levels necessary
to drive a 75 Ω load. The output stage utilizes negative feed-
back to implement a differential 75 Ω output impedance. This
eliminates the need for external matching resistors needed in
typical video (or video filter) termination requirements.
SPI Programming and Gain Adjustment
Gain programming of the AD8323 is accomplished using a
serial peripheral interface (SPI) and three digital control lines,
DATEN, SDATA, and CLK. To change the gain, eight bits of
data are streamed into the serial shift register through the
SDATA port. The SDATA load sequence begins with a falling
edge on the DATEN pin, thus activating the CLK line. Although
the CLK line is now activated, no change in gain is yet observed
at the output of the amplifier. With the CLK line activated, data
on the SDATA line is clocked into the serial shift register Most
Significant Bit (MSB) first, on the rising edge of each CLK
pulse. Because only a 7-bit shift register is used, the MSB of the
8-bit word is a “don’t care” bit and is shifted out of the register
on the eighth clock pulse. A rising edge on the DATEN line
latches the contents of the shift register into the attenuator core
resulting in a well controlled change in the output signal level.
The serial interface timing for the AD8323 is shown in Figures 2
and 3. The programmable gain range of the AD8323 is –26 dB
to +27.5 dB and scales 0.7526 dB per least significant bit (LSB).
Because the AD8323 was characterized with a TOKO transformer,
the stated gain values already take into account the losses associ-
ated with the transformer.
The gain transfer function is as follows:
where A
of the 8-bit word.
Valid gain codes are from 0 to 71. Figure 4 shows the gain
characteristics of the AD8323 for all possible values in an 8-bit
word. Note that maximum gain is achieved at Code 71. From
Code 72 through 127 the 5.25 dB of attenuation from the ver-
nier stage is being applied over every eight codes, resulting in
the sawtooth characteristic at the top of the gain range. Because
the eighth bit is a “don’t care” bit, the characteristic for codes 0
through 127 repeats from Codes 128 through 255.
Input Bias, Impedance, and Termination
The V
V
differential input impedance is approximately 1600 Ω while the
single-ended input impedance is 800 Ω. If the AD8323 is being
operated in a single-ended input configuration with a desired
input impedance of 75 Ω, the V
terminated as shown in Figure 5. If an input impedance other
than 75 Ω is desired, the values of R1 and R2 in Figure 5 can be
calculated using the following equations:
A
CC
V
= 27.5 dB – (0.7526 dB × (71 – CODE)) for 0 ≤ CODE ≤ 71
/2, therefore the input signal should be ac-coupled. The
Z
R
IN+
IN
2
–14
–21
–28
V
=
28
21
14
–7
= 1 800
7
0
is the gain in dB and CODE is the decimal equivalent
and V
Z
0
R
IN
R
32
IN–
1
Z
R1 = 82.5
IN
inputs have a dc bias level of approximately
= 75
64
GAIN CODE – Decimal
96
R2 = 39.2
IN+
128
and V
–
+
AD8323
160
IN–
192
inputs should be
AD8323
224
256