STEVAL-TLL004V1 STMicroelectronics, STEVAL-TLL004V1 Datasheet - Page 16

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STEVAL-TLL004V1

Manufacturer Part Number
STEVAL-TLL004V1
Description
BOARD EVAL FLASH DRIVER STCF03
Manufacturer
STMicroelectronics
Datasheets

Specifications of STEVAL-TLL004V1

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-8431
Introduction
7.6
Figure 7.
7.7
Figure 8.
16/35
Byte format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first. One data bit is transferred during each clock
pulse. The data on the SDA line must remain stable during the HIGH period of the clock
pulse. Any change in the SDA line at this time will be interpreted as a control signal.
Bit transfer
Acknowledge
The master (microprocessor) puts a resistive HIGH level on the SDA line during the
acknowledge clock pulse (see
pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is
stable LOW during this clock pulse. The peripheral which has been addressed has to
generate an acknowledge pulse after the reception of each byte, otherwise the SDA line
remains at the HIGH level during the ninth clock pulse duration. In this case the master
transmitter can generate the STOP information in order to abort the transfer. The STCF03
won't generate the acknowledge if the V
Acknowledge on I²C Bus
Figure
Doc ID 13169 Rev 7
8). The peripheral (STCF03) that acknowledges has to
I
supply is below the undervoltage lockout threshold.
STCF03

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