Z8F6421AN00ZEM Zilog, Z8F6421AN00ZEM Datasheet - Page 183

• Manufacturer Part Number: Z8F6421AN00ZEM
• Description: KIT ICE Z8 ENCORE 64K 44LQFP
• Manufacturer: Zilog
• Series: Z8 Encore!®r
• Type: In-Circuit Emulator Systemr

Specifications of Z8F6421AN00ZEM

• Contents: Emulator Board, Cables, Software and Documentation
• For Use With/related Products: Z8 Encore! 44-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3392

Table 85. DMA_ADC Status Register (DMAA_STAT)
PS019921-0308
BITS
FIELD
RESET
R/W
ADDR
DMA Status Register
7
0101 = ADC Analog Inputs 0-5 updated.
0110 = ADC Analog Inputs 0-6 updated.
0111 = ADC Analog Inputs 0-7 updated.
1000 = ADC Analog Inputs 0-8 updated.
1001 = ADC Analog Inputs 0-9 updated.
1010 = ADC Analog Inputs 0-10 updated.
1011 = ADC Analog Inputs 0-11 updated.
1100-1111 = Reserved.
The DMA Status register
ated the interrupt and the ADC Analog Input that is currently undergoing conversion.
Reads from this register reset the Interrupt Request Indicator bits (IRQA, IRQ1, and
IRQ0) to 0. Therefore, software interrupt service routines that read this register must pro-
cess all three interrupt sources from the DMA.
CADC[3:0]—Current ADC Analog Input
This field identifies the Analog Input that the ADC is currently converting.
Reserved
This bit is reserved and must be 0.
IRQA—DMA_ADC Interrupt Request Indicator
This bit is automatically reset to 0 each time a read from this register occurs.
0 = DMA_ADC is not the source of the interrupt from the DMA Controller.
1 = DMA_ADC completed transfer of data from the last ADC Analog Input and generated
an interrupt.
IRQ1—DMA1 Interrupt Request Indicator
This bit is automatically reset to 0 each time a read from this register occurs.
0 = DMA1 is not the source of the interrupt from the DMA Controller.
1 = DMA1 completed transfer of data to/from the End Address and generated an interrupt.
IRQ0—DMA0 Interrupt Request Indicator
This bit is automatically reset to 0 each time a read from this register occurs.
6
CADC[3:0]
5
(Table 85
4
on page 169) indicates the DMA channel that gener-
FBFH
R
0
Reserved
3
Z8 Encore! XP
IRQA
2
Direct Memory Access Controller
Product Specification
IRQ1
1
®
F64XX Series
IRQ0
0
169