Z8F6421AN00ZEM Zilog, Z8F6421AN00ZEM Datasheet - Page 129

• Manufacturer Part Number: Z8F6421AN00ZEM
• Description: KIT ICE Z8 ENCORE 64K 44LQFP
• Manufacturer: Zilog
• Series: Z8 Encore!®r
• Type: In-Circuit Emulator Systemr

Specifications of Z8F6421AN00ZEM

• Contents: Emulator Board, Cables, Software and Documentation
• For Use With/related Products: Z8 Encore! 44-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3392

PS019921-0308
01 = The UART generates an interrupt request only on received address bytes.
10 = The UART generates an interrupt request when a received address byte matches
11 = The UART generates an interrupt request on all received data bytes for which
MPEN—MULTIPROCESSOR (9-bit) Enable
This bit is used to enable MULTIPROCESSOR (9-bit) mode.
0 = Disable MULTIPROCESSOR (9-bit) mode.
1 = Enable MULTIPROCESSOR (9-bit) mode.
MPBT—MULTIPROCESSOR Bit Transmit
This bit is applicable only when MULTIPROCESSOR (9-bit) mode is enabled.
0 = Send a 0 in the multiprocessor bit location of the data stream (9
1 = Send a 1 in the multiprocessor bit location of the data stream (9
DEPOL—Driver Enable Polarity
0 =
1 =
BRGCTL—Baud Rate Control
This bit causes different UART behavior depending on whether the UART receiver is
enabled (
When the UART receiver is not enabled, this bit determines whether the Baud Rate Gener-
ator issues interrupts.
0 = Reads from the Baud Rate High and Low Byte registers return the BRG Reload Value
1 = The Baud Rate Generator generates a receive interrupt when it counts down to 0.
Reads from the Baud Rate High and Low Byte registers return the current BRG count
value.
When the UART receiver is enabled, this bit allows reads from the Baud Rate Registers to
return the BRG count value instead of the Reload Value.
0 = Reads from the Baud Rate High and Low Byte registers return the BRG Reload Value.
1 = Reads from the Baud Rate High and Low Byte registers return the current BRG
RDAIRQ—Receive Data Interrupt Enable
0 = Received data and receiver errors generates an interrupt request to the Interrupt
1 = Received data does not generate an interrupt request to the Interrupt Controller.
IREN—Infrared Encoder/Decoder Enable
0 = Infrared Encoder/Decoder is disabled. UART operates normally operation.
count value. Unlike the Timers, there is no mechanism to latch the High Byte
Controller.
DE
DE
when the Low Byte is read.
Only receiver errors generate an interrupt request.
the value stored in the Address Compare Register and on all successive data
bytes until an address mismatch occurs.
the most recent address byte matched the value in the Address Compare Register.
signal is Active High.
signal is Active Low.
REN
= 1 in the UART Control 0 Register).
Z8 Encore! XP
Product Specification
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bit).
bit).
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F64XX Series
UART
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