MSC8144ADS Freescale Semiconductor, MSC8144ADS Datasheet - Page 31

• Manufacturer Part Number: MSC8144ADS
• Description: ADS FOR MSC8144 DEVICE
• Manufacturer: Freescale Semiconductor
• Type: DSPr

Specifications of MSC8144ADS

• Contents: AMC Card, Power Supply, Cables, USB TAP, Hardware and Documentation
• For Use With/related Products: MSC8144
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Electrical Characteristics
2.5.2
Serial RapidIO DC Electrical Characteristics
DC receiver logic levels are not defined since the receiver is AC-coupled.
2.5.2.1
DC Requirements for SerDes Reference Clocks
The SerDes reference clocks SRIO_REF_CLK and SRIO_REF_CLK are AC-coupled differential inputs. Each differential
clock input has an internal 50 Ω termination to
. The reference clock must be able to drive this termination. The
GND
SXC
recommended minimum operating voltage is –0.4 V; the recommended maximum operating voltage is 1.32 V; and the
maximum absolute voltage is 1.72 V.
The maximum average current allowed in each input is 8 mA. This current limitation sets the maximum common mode input
voltage to be less than 0.4 V (0.4 V/50 Ω = 8 mA) while the minimum common mode input level is
. For example, a
GND
SXC
clock with a 50/50 duty cycle can be driven by a current source output that ranges from 0 mA to 16 mA (0–0.8 V). The input is
AC-coupled internally, so, therefore, the exact common mode input voltage is not critical.
Note:
This internal AC-couple network does not function correctly with reference clock frequencies below 90 MHz.
If the device driving the SRIO_REF_CLK inputs cannot drive 50 Ω to GND
, or if it exceeds the maximum input current
SXC
limitations, then it must use external AC-coupling. The minimum differential peak-to-peak amplitude of the input clock is 0.4 V
(0.2 V peak-to-peak per phase). The maximum differential peak-to-peak amplitude of the input clock is 1.6 V peak-to-peak (see
Figure
5. The termination to GND
allows compatibility with HCSL type reference clocks specified for PCI-Express
SXC
applications. Many other low voltage differential type outputs can be used but will probably need to be AC-coupled due to the
limited common mode input range. LVPECL outputs can produce too large an amplitude and may need to be source terminated
with a divider network to reduce the amplitude. The amplitude of the clock must be at least a 400 mV differential peak-peak for
single-ended clock. If driven differentially, each signal wire needs to drive 100 mV around common mode voltage. The
differential reference clock (SRIO_REF_CLK/ SRIO_REF_CLK) input is HCSL-compatible DC coupled or LVDS-compatible
with AC-coupling.
SRIO_REF_CLK
50 Ω
GND
SXC
50 Ω
SRIO_REF_CLK
Figure 5. SerDes Reference Clocks Input Stage
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Freescale Semiconductor
31