CY8CKIT-001 Cypress Semiconductor Corp, CY8CKIT-001 Datasheet - Page 47

KIT DEV FOR PSOC3/5

CY8CKIT-001

Manufacturer Part Number
CY8CKIT-001
Description
KIT DEV FOR PSOC3/5
Manufacturer
Cypress Semiconductor Corp
Series
PSoC® CapSenser
Type
MCUr
Datasheets

Specifications of CY8CKIT-001

Contents
Board, CD, CY8C29 & CY8C38 Modules, MiniProg3 Programmer/Debugger, Power Supply
Processor To Be Evaluated
CY8C29, CY8C38
Interface Type
RS-232, USB, JTAG
Operating Supply Voltage
3.3 V, 5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
PSoC 1, PSoC 3 and PSoC 5
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
428-2961

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY8CKIT-001A
Manufacturer:
Cypress Semiconductor
Quantity:
135
3.1.3.2
CY8CKIT-001 PSoC Development Kit Guide, Doc. # 001-48651 Rev. **
main.c
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This file provides source code for the ADC to LCD with DAC and UART example
project. The firmware takes a voltage output from a potentiometer and
displays the ADC raw count on an LCD. The raw count is also transmitted
serially. The raw count also determines the clock divider value of the clock
driving the DAC update rate.
PGA_1 Settings:(The PGA buffers the potentiometer voltage on P0.1 into the ADC)
LCD_1 Settings:
DelSig_1 Settings:
The ADC can read full range values from 0-5V, if the Ref Mux setting is
selected as (Vdd/2)+/- (Vdd/2) and Vdd = 5V. The ADC is configured for a
resolution of 8 bits, this is achieved by selecting the appropriate
configuration when placing the UM.
Counter8_1 Settings:
The Counter8_1 controls the update rate of the DAC. The DAC is updated
during ever TerminalCount ISR. The frequency of the TerminalCount ISR is
determined by the Counter Input Clock divided by the (Period value +1).
The Period Value of the counter is changed by the ADC reading. Thus the
frequency of the TerminalCount ISR can range from 125kHz (Period Value=1)
to 977Hz (Period Value = 255)
Gain
Input
Reference = AGND
AnalogBus = Disable
LCDPort
BarGraph = Disable
DataFormat
DataClock
ClockPhase
PosInput
NegInput
NegInputGain = Disconnected
PWM Output
PulseWidth
Clock
ClockSync
Enable
CompareOut
TerminalCountOut = None
= Port_2
= 1
= AnalogColumn_InputMUX_0
= Unsigned
= VC2 //VC2 = 24MHz/16/16 = 250kHz
= Normal
= ACB00 (PGA_1)
= ACB00
= None
= N/A
= VC2 // VC2 = 24MHz/16/16 = 250kHz
= Sync to SysClk
= High
= None
*Note this parameter is not used
*Note this parameter is not used
(P0.1)
Sample Projects
43
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