HW-V5-ML506-UNI-G Xilinx Inc, HW-V5-ML506-UNI-G Datasheet - Page 8

• Manufacturer Part Number: HW-V5-ML506-UNI-G
• Description: EVALUATION PLATFORM VIRTEX-5
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 SXTr
• Type: DSPr

Specifications of HW-V5-ML506-UNI-G

• Contents: Evaluation Platform, DVI Adapter and CompactFlash Card
• Silicon Manufacturer: Xilinx
• Features: JTAG Programming Interface, Platform Flash, External Clocking
• Kit Contents: Board, Cable, PSU, CD, Docs
• Silicon Family Name: Virtex-5
• Silicon Core Number: XC5VSX50TFFG1136
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: XC5VSX50TFFG1136
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Preface: About This Guide
Additional Support Resources
Typographical Conventions
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To search the database of silicon and software questions and answers, or to create a
technical support case in WebCase, see the Xilinx website at:
http://www.xilinx.com/support.
This document uses the following typographical conventions. An example illustrates each
convention.
Italic font
Underlined Text
Virtex-5 FPGA RocketIO GTP/GTX Transceiver User Guide
This guide describes the RocketIO™ GTP/GTX transceivers available in the Virtex-5
LXT and SXT platform devices.
Virtex-5 FPGA Tri-Mode Ethernet Media Access Controller User Guide
This user guide describes the dedicated Tri-Mode Ethernet Media Access Controller
available in the Virtex-5 LXT and SXT platform devices.
Virtex-5 FPGA Integrated Endpoint Block User Guide for PCI Express Designs
This user guide describes the integrated Endpoint blocks in the Virtex-5 LXT and SXT
platform devices for PCI Express® designs.
XtremeDSP Design Considerations
This guide describes the XtremeDSP. slice and includes reference designs for using the
DSP48E.
Virtex-5 FPGA Configuration User Guide
This all-encompassing configuration guide includes chapters on configuration
interfaces (serial and SelectMAP), bitstream encryption, Boundary-Scan and JTAG
configuration, reconfiguration techniques, and readback through the SelectMAP and
JTAG interfaces.
Virtex-5 FPGA System Monitor User Guide
The System Monitor functionality available in all the Virtex-5 devices is outlined in
this guide.
Virtex-5 FPGA Packaging and Pinout Specification
This specification includes the tables for device/package combinations and maximum
I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and
thermal specifications.
Convention
References to other documents
Emphasis in text
Indicates a link to a web page.
www.xilinx.com
Meaning or Use
ML505/ML506/ML507 Evaluation Platform
See the Virtex-5 Configuration
Guide for more information.
The address (F) is asserted after
clock event 2.
http://www.xilinx.com/virtex5
UG347 (v3.1.1) October 7, 2009
Example
R