HW-V5-ML506-UNI-G Xilinx Inc, HW-V5-ML506-UNI-G Datasheet - Page 37

EVALUATION PLATFORM VIRTEX-5

HW-V5-ML506-UNI-G

Manufacturer Part Number
HW-V5-ML506-UNI-G
Description
EVALUATION PLATFORM VIRTEX-5
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Type
DSPr
Datasheet

Specifications of HW-V5-ML506-UNI-G

Contents
Evaluation Platform, DVI Adapter and CompactFlash Card
Silicon Manufacturer
Xilinx
Features
JTAG Programming Interface, Platform Flash, External Clocking
Kit Contents
Board, Cable, PSU, CD, Docs
Silicon Family Name
Virtex-5
Silicon Core Number
XC5VSX50TFFG1136
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
XC5VSX50TFFG1136
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HW-V5-ML506-UNI-G
Manufacturer:
XILINX
0
ML505/ML506/ML507 Evaluation Platform
UG347 (v3.1.1) October 7, 2009
34. IIC Fan Controller and Temperature/Voltage Monitor
35. Piezo
36. VGA Input Video Codec
R
Onboard temperature and voltage monitoring and control is handled by an Analog
Devices ADT7476A chip. This chip is controlled via IIC and can provide the following
functions:
Connector J31 is a keyed three-pin fan header similar to those found in computers. It is
designed to support a 5V DC fan. To bypass the fan controller chip and operate the fan at
full speed, the user can populate connector J32.
For high-power operating conditions, a heatsink and/or fan for the FPGA can be
accommodated on the board. The board does not ship with a heatsink/fan unit but can
accommodate one (for example, Calgreg Electronics Smart-CLIP family of heatsink/fan
assemblies).
A piezo audio transducer
to be played. The piezo is driven by a transistor controlled by the FPGA.
Table 1-19: Piezo Connection
The DB15HD connector (P8) on the board supports connectivity to an external VGA
source. The VGA input codec circuitry utilizes an Analog Devices AD9980 device (U19).
The AD9980 is an 8-bit 95 MSPS interface optimized for capturing YPbPr video and RGB
graphics signals. Its 95 MSPS encode rate supports HDTV video modes and graphics
resolutions up to XGA (1024 × 768 at 85 Hz). The Analog Devices AD9980 device is
controlled by way of the Video IIC bus.
Table 1-20
Table 1-20: VGA Interface Connections
VGA_IN_RED0
VGA_IN_RED1
VGA_IN_RED2
VGA_IN_RED3
VGA_IN_RED4
Measure the voltage of 5V, 3.3V, 1.8V, and 1.0V supplies
Measure FPGA temperature via DXP/DXN pins on the FPGA
Measure ambient temperature
Read power good status signals from 2.5V linear regulators
PWM control of fan speed
Fan Tachometer readings
Generate interrupts/alarms based on readings
Name
piezo
Net Name
shows the connections for the VGA input video codec.
FPGA Pin
G30
www.xilinx.com
(Table
FPGA Pin
AG5
AH5
1-19) is provided to allow simple beeps, tones, and songs
AF5
W7
V7
Detailed Description
37

Related parts for HW-V5-ML506-UNI-G