MPC8378E-MDS-PB Freescale Semiconductor, MPC8378E-MDS-PB Datasheet - Page 111

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MPC8378E-MDS-PB

Manufacturer Part Number
MPC8378E-MDS-PB
Description
BOARD PROCESSOR FOR MDS S
Manufacturer
Freescale Semiconductor
Type
MPUr
Datasheets

Specifications of MPC8378E-MDS-PB

Contents
Board
For Use With/related Products
MPC8378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
As described in
configuration word low and the CFG_CLKIN_DIV configuration input signal select the ratio between the
primary clock input (CLKIN or PCI_CLK) and the internal coherent system bus clock (csb_clk).
and
CLKIN/PCI_SYNC_IN ratios.
The RCWLR[SVCOD] denotes the system PLL VCO internal frequency as shown in
Freescale Semiconductor
CFG_CLKIN_DIV
Table 74
at Reset
High
High
High
High
High
show the expected frequency values for the CSB frequency for select csb_clk to
1
Section 22, “Clocking,”
RCWLR[SVCOD]
RCWLR[SPMF]
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
0111–1111
0000
0001
0010
0011
0100
0101
0110
00
01
10
11
SPMF
0010
0011
0100
0101
0110
Table 73. CSB Frequency Options for Host Mode
Table 71. System PLL Multiplication Factors
Table 72. System PLL VCO Divider
The LBIUCM, DDRCM, and SPMF parameters in the reset
Input Clock Ratio
csb_clk :
2 : 1
3 : 1
4 : 1
5 : 1
6 : 1
2
System PLL Multiplication Factor
150
25
VCO Division Factor
Input Clock Frequency (MHz)
csb_clk Frequency (MHz)
× 7 to × 15
Reserved
Reserved
× 2
× 3
× 4
× 5
× 6
4
8
2
1
33.33
133
167
200
Table
72.
66.67
Table 73
2
133
200
267
333
400
Clocking
111

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