DK-SI-4SGX230N Altera, DK-SI-4SGX230N Datasheet - Page 18

• Manufacturer Part Number: DK-SI-4SGX230N
• Description: KIT DEV STRATIX IV 4SGX230N/C2
• Manufacturer: Altera
• Series: Stratix® IV GXr
• Type: FPGAr

Specifications of DK-SI-4SGX230N

• Contents: Board, Cables, CD, Power Supply
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2592; DK-SI-4SGX230N/C2

6–4
Transceiver Signal Integrity Development Kit, Stratix IV GX Edition User Guide
1
Table 6–2. Jumper Header Connections
The following list defines the analog setting parameters in the control panel window:
Resets
The following list describes the available resets:
After the System Reset is asserted, the DataChk Status may show unsynced for some
channels due to the asynchronous nature of the reset. Asserting the Data Patrst
synchronizes the error checker to the transmitted data.
Help
The Help button displays the image of the Stratix IV signal integrity board and also
highlights the channel locations and their data rates based on the .sof loaded.
Power Down
Turn on Powerdown to power down the transceiver block.
Serial Loopback
Serial loopback is available for all the channels and can be controlled during run time.
After the serial loopback status in the interface changes, the DataChk Status field
may show unsynced for some channels due to the asynchronous nature of the serial
loopback signal. The Data Patrst should be asserted in this case to synchronize the
error checker with the transmitted data.
In the signal_integrity_demo1.sof, internal serial loopback is not enabled for the two
channels configured in PCI Express (PIPE) mode. Therefore, you must connect an
external SMA cable between the transmit output and the receive input to loopback the
data.
Pins 1 and 2
Note to
(1) Before you power up the board, specify the VCCHTX and the VCCA jumper settings.
Parameter
VOD
EQ
Gain
PE
Reset
System
Error
Table
Jumper Header Connection
6–2:
VCCHTX (Volt)
Description
Reset for the transceiver.
Reset for all the error counters to zero.
Description
differential output driver voltage.
equalization.
DC gain.
preemphasis/deemphasis.
pre, 1stpost, and 2ndpost settings represent different taps.
1.4 V
Chapter 6: Stratix IV GX Transceiver Signal Integrity Demonstration
(Note 1)
Pins 2 and 3
Running the Demonstration Application and Test Designs
Jumper Header Connection
VCCA_L/R (Volt)
© February 2009 Altera Corporation
3.0 V