KIT908E624DWBEVB Freescale Semiconductor, KIT908E624DWBEVB Datasheet - Page 12

• Manufacturer Part Number: KIT908E624DWBEVB
• Description: KIT EVAL 908E624 TRPL W/MCU/LIN
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of KIT908E624DWBEVB

• Contents: *
• Silicon Manufacturer: Freescale
• Core Architecture: HC08
• Core Sub-architecture: HC08
• Silicon Core Number: MC68HC908
• Silicon Family Name: HC08E
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 4. Dynamic Electrical Characteristics
microcontroller chip. Characteristics noted under conditions 9.0 V
Typical values noted reflect the approximate parameter mean at T
12
908E624
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
LIN PHYSICAL LAYER
Notes
Driver Characteristics for Normal Slew Rate
Dominant Propagation Delay TXD to LIN
Dominant Propagation Delay TXD to LIN
Recessive Propagation Delay TXD to LIN
Recessive Propagation Delay TXD to LIN
Propagation Delay Symmetry: t
Propagation Delay Symmetry: t
Driver Characteristics for Slow Slew Rate
Dominant Propagation Delay TXD to LIN
Dominant Propagation Delay TXD to LIN
Recessive Propagation Delay TXD to LIN
Recessive Propagation Delay TXD to LIN
Propagation Delay Symmetry: t
Propagation Delay Symmetry: t
Driver Characteristics for Fast Slew Rate
LIN High Slew Rate (Programming Mode)
Receiver Characteristics and Wake-Up Timings
Receiver Dominant Propagation Delay
Receiver Recessive Propagation Delay
Receiver Propagation Delay Symmetry
Bus Wake-Up Deglitcher
Bus Wake-Up Event Reported
17.
18.
19.
20.
21.
All characteristics are for the analog chip only. Please refer to the 68HC908EY16 data sheet for characteristics of the
V
to LIN signal threshold defined at each parameter.
See
See
Measured between LIN signal threshold V
t
rise time is strongly dependent upon the decoupling capacitor at VDD terminal.
WAKE
SUP
Figure
Figure
from 7.0 V to 18 V, bus load R0 and C0 1.0 nF / 1.0 kΩ, 6.8 nF / 660 Ω, 10 nF / 500 Ω. Measurement thresholds: 50% of TXD signal
is typically 2 internal clock cycles after LIN rising edge detected. See
6, page 15.
7, page 16.
Characteristic
(21)
DOM-MIN
DOM-
DOM-
DOM-MAX
MAX
MIN
(20)
DYNAMIC ELECTRICAL CHARACTERISTICS
(20)
- t
- t
- t
- t
(17)
REC-
REC-
REC-
REC-
(17)
,
(19)
,
MAX
MAX
MIN
MIN
IL
(18)
or V
IH
and 50% of RXD signal.
≤
A
V
= 25°C under nominal conditions unless otherwise noted.
SUP
t
t
t
≤
t
t
t
t
t
t
DOM-
DOM-
REC-
REC-
PROP
Symbol
DOM-
DOM-
SR
REC-
REC-
t
t
16 V, - 40°C
R-SYM
WAKE
Figure 8
dt1s
dt2s
t
t
dt1
dt2
RH
FAST
RL
MAX
MAX
MAX
MAX
MIN
MIN
MIN
MIN
WL
and
Figure
≤
-10.44
- 2.0
Min
- 22
Analog Integrated Circuit Device Data
T
35
—
—
—
—
—
—
—
—
—
—
—
—
—
—
J
≤
9, page 16. In Sleep mode the V
125°C unless otherwise noted.
Typ
3.5
3.5
15
20
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Freescale Semiconductor
Max
100
100
100
100
150
6.0
6.0
2.0
50
50
50
50
—
11
—
23
—
—
V / μs
Unit
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
DD