EDK2329 Renesas Electronics America, EDK2329 Datasheet - Page 8

• Manufacturer Part Number: EDK2329
• Description: DEV EVALUATION KIT H8S/2329
• Manufacturer: Renesas Electronics America
• Series: H8®r
• Type: MCUr

Specifications of EDK2329

• Contents: 2G (Second-generation) Evaluation Board, HEW debugger support, Cable and CD-ROM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: H8S/2329
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant

4.4. M
Table 4-4 illustrates the EDK memory map for mode 6.
4.5. SRAM A
External access timing is defined by several registers, allowing different types of devices to be addressed. The registers for
the selection of wait states and signal extensions are given below with recommended values for the EDK.
Please refer to the hardware manual for the microcontroller for more information on these register settings.
4.6. LED
The EDK has four red LEDs. The function of each LED is clearly marked on the silk screen of the PCB. Please refer to the
board layout diagram for position information (Figure 3.1).
When the board is connected to a power source the Power (PWR) led will illuminate. The Boot mode indication LED will
illuminate when the microcontroller has been placed into Boot mode. Please see section 5.7 for more details of this function.
There are two LEDs dedicated for user control these are marked USR1 and USR2. Each LED will illuminate when the port
pin is in a logical high state.
The user LEDs are connected to the following ports:
Register
ABWCR
PADDR
PBDDR
PCDDR
PGDDR
ASTCR
WCRL
BCRH
EMORY
S
M
CCESS
H’FEBA
Address
H’FEBB
H’FED0
H’FED1
H’FED4
H’FEB9
H’FEBF
H’FED3
AP
H’00000000
H’0000FFFF
H’00010000
H’0005FFFF
H’00060000
H’0007FFFF
H’00080000
H’00FF73FF
H’00FF7400
H’00FF7BFF
H’00FF7C00
H’00FFFBFF
H’00FFFC00
H’00FFFE4F
H’00FFFE50
H’00FFFF07
H’00FFFF08
H’00FFFF27
H’00FFFF28
H’00FFFFFF
T
Identifier
IMING
USR1
USR2
LED
Setting for EDK
Recommended
Section Start
Section End
H’D0
H’FD
H’F0
H’FF
H’FF
H’FF
H’07
H’01
Port
Pin
P21
P22
T
ABLE
T
ABLE
Microcontroller
T
Bus Width Control Register. Enables 16 bit access for CS0 space.
Access State Control Register. Initialised to 3-state access.
16b R/W access. Specifies idle cycles.
Port A Data Direction Register. Enables address signals A(18:16) for output.
Port B Data Direction Register. Enables address signals A(15:8) for output.
Port C Data Direction Register. Enables address signals A(7:0) for output.
Port G Data Direction Register. CSn(0) output pin.
16b R/W access. Specifies 1 wait cycle for CS0 space.
4-5: SRAM A
ABLE
4-4: M
Pin
78
77
4-6: LED P
EMORY
CCESS
On-chip ROM
On-chip ROM / External Address Space
Reserved area
External Address Space
Reserved Area
On-chip RAM
External Address Space
Internal IO Registers
External Address Space
Internal IO Registers
M
ORT
AP
C
(D
C
ONTROL
P22 / PO2 / TIOCC3 / TMRI0
EFAULT
ONNECTIONS
Pin Functions on Port Pin
Section Allocation
P21 / PO1 / TIOCB3
R
M
EGISTERS
ODE
6)
Function
8